18398926. SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)
Contents
SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME
Organization Name
Inventor(s)
Jingfan Yang of Suzhou Industrial Park (CN)
Peng Zhang of Suzhou Industrial Park (CN)
SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME - A simplified explanation of the abstract
This abstract first appeared for US patent application 18398926 titled 'SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME
The semiconductor package described in the patent application consists of a lower-layer structure with a substrate, a first chip connected to the substrate via bumps, an upper-layer structure made of a first molding material covering the inactive surface of the first chip, and a middle-layer structure with at least one interlayer made of a second molding material different from the first.
- The semiconductor package includes a unique three-layer structure for enhanced performance and durability.
- The first chip is electrically connected to the substrate through bumps, ensuring efficient functionality.
- The upper-layer structure made of a first molding material provides protection to the first chip.
- The middle-layer structure, made of a different molding material, fills the space between the lower and upper layers, adding structural integrity.
- The combination of these layers results in a robust semiconductor package suitable for various applications.
Potential Applications: - This semiconductor package can be used in electronic devices such as smartphones, laptops, and tablets. - It can also be applied in automotive electronics, industrial machinery, and medical devices.
Problems Solved: - The semiconductor package addresses the need for reliable electrical connections in compact electronic devices. - It provides protection to the sensitive components of the chip, ensuring longevity and performance.
Benefits: - Enhanced electrical connectivity and performance. - Improved durability and protection for semiconductor components. - Versatile applications in various industries.
Commercial Applications: Title: Advanced Semiconductor Packaging Technology for Enhanced Device Performance This technology can be commercialized by semiconductor manufacturers for producing high-performance electronic devices with improved reliability and durability. The market implications include increased demand for advanced semiconductor packaging solutions in the consumer electronics, automotive, and healthcare industries.
Prior Art: Readers interested in exploring prior art related to semiconductor packaging technologies can start by researching existing patents in the field of semiconductor packaging, interlayer materials, and chip protection methods.
Frequently Updated Research: Researchers in the semiconductor industry are constantly working on developing new materials and techniques to improve semiconductor packaging technologies. Stay updated on the latest advancements in interlayer materials, chip protection methods, and semiconductor packaging design for cutting-edge innovations in electronic devices.
Questions about Semiconductor Packaging Technology: 1. How does the three-layer structure of the semiconductor package contribute to its overall performance and durability? 2. What are the key differences between the first and second molding materials used in the upper and middle layers of the semiconductor package?
Original Abstract Submitted
Provided are semiconductor packages and methods of manufacturing the same. A semiconductor package includes a lower-layer structure including a substrate, a first chip including bumps on an active surface thereof, the first chip being electrically connected to the substrate via the bumps, an upper-layer structure formed of a first molding material, the first molding material covering an inactive surface of the first chip opposite and surrounding at least a portion of a lateral surface of the first chip, the inactive surface of the first chip being opposite to the active surface of the first chip, and a middle-layer structure including at least one interlayer, the at least one inter layer being formed of a second molding material different from the first molding material, the middle-layer structure being between the lower-layer and upper-layer structures and filling a space between the lower-layer and upper-layer structures.
