TRENCH AND PIER ARCHITECTURES FOR THREE-DIMENSIONAL MEMORY ARRAYS: abstract simplified (17714771)

• This abstract for appeared for patent application number 17714771 Titled 'TRENCH AND PIER ARCHITECTURES FOR THREE-DIMENSIONAL MEMORY ARRAYS'

Simplified Explanation

This abstract describes methods, systems, and devices for creating trench and pier architectures in three-dimensional memory arrays. These architectures involve the formation of pier structures in contact with alternating layers of materials deposited on a substrate. These pier structures provide support for subsequent processing steps. The memory die includes alternating layers of a first and second material, which can be shaped into different cross-sectional patterns. The pier structures are formed in contact with these patterns, and when one of the materials is removed to create voids, the pier structures help maintain the shape of the remaining material. These pier structures can be formed within or along trenches or other features aligned in the direction of the memory array, allowing for self-alignment in subsequent operations.

Original Abstract Submitted

Methods, systems, and devices for trench and pier architectures for three-dimensional memory arrays are described. A semiconductor device (e.g., a memory die) may include pier structures formed in contact with features formed from alternating layers of materials deposited over a substrate, which may provide support for subsequent processing. For example, a memory die may include alternating layers of a first material and a second material, which may be formed into various cross-sectional patterns. Pier structures may be formed in contact with the cross sectional patterns such that, when either the first material or the second material is removed to form voids, the pier structures may provide mechanical support of the cross-sectional pattern of the remaining material. In some examples, such pier structures may be formed within or along trenches or other features aligned along a direction of a memory array, which may provide a degree of self-alignment for subsequent operations.