18628562. MEMORY WITH PROGRAMMABLE REFRESH ORDER AND STAGGER TIME simplified abstract (Lodestar Licensing Group LLC)

MEMORY WITH PROGRAMMABLE REFRESH ORDER AND STAGGER TIME

Organization Name

Lodestar Licensing Group LLC

Inventor(s)

Vaughn N. Johnson of Boise ID (US)

Debra M. Bell of Boise ID (US)

Miles S. Wiscombe of Boise ID (US)

Brian T. Pecha of Boise ID (US)

Kyle Alexander of Boise ID (US)

MEMORY WITH PROGRAMMABLE REFRESH ORDER AND STAGGER TIME - A simplified explanation of the abstract

This abstract first appeared for US patent application 18628562 titled 'MEMORY WITH PROGRAMMABLE REFRESH ORDER AND STAGGER TIME

Simplified Explanation

Memory devices and systems with programmable refresh order and stagger times are disclosed. In one embodiment, a memory device includes two memory bank groups and is configured to perform refresh operations at different times in response to a refresh command, while still allowing read or write operations to be performed concurrently.

• Memory device includes programmable refresh order and stagger times
• Two memory bank groups
• Refresh operations performed at different times in response to refresh command
• Read or write operations can be performed concurrently with refresh operations

Potential Applications

This technology can be applied in various memory systems where efficient refresh operations are required, such as in servers, data centers, and high-performance computing systems.

Problems Solved

This technology addresses the issue of memory refresh operations causing delays in read or write operations, leading to improved overall memory performance and efficiency.

Benefits

• Improved memory performance
• Efficient refresh operations
• Concurrent read or write operations

Commercial Applications

The technology can be utilized in servers, data centers, and high-performance computing systems to enhance memory performance and efficiency, potentially leading to faster data processing and improved system reliability.

Questions about Memory Devices with Programmable Refresh Order and Stagger Times

1. How does the programmable refresh order in memory devices improve overall performance? 2. What are the potential drawbacks of implementing stagger times in memory systems?

Original Abstract Submitted

Memory devices and systems with programmable refresh order and stagger times are disclosed herein. In one embodiment, a memory device includes a first memory bank group and a second memory bank group. The memory device is configured, in response to a refresh command, to perform a first refresh operation on the first memory bank group at a first time and a second refresh operation on the second memory bank group at a second time after the first time. The memory device is further configured to perform, in response to a read or write command, a read or write operation on the first memory bank group, the second memory bank group, or both the first and second memory bank groups after beginning the first refresh operation and before completing the second refresh operation.