IMPROVED CONTACT RESISTANCE BETWEEN VIA AND CONDUCTIVE LINE

Organization Name

Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor(s)

Chun-Yuan Chen of Hsinchu (TW)

Shih-Chuan Chiu of Hsinchu (TW)

Jia-Chuan You of Taoyuan County (TW)

Chia-Hao Chang of Hsinchu City (TW)

Tien-Lu Lin of Hsinchu County (TW)

Yu-Ming Lin of Hsinchu City (TW)

IMPROVED CONTACT RESISTANCE BETWEEN VIA AND CONDUCTIVE LINE - A simplified explanation of the abstract

This abstract first appeared for US patent application 18447084 titled 'IMPROVED CONTACT RESISTANCE BETWEEN VIA AND CONDUCTIVE LINE

Simplified Explanation

The patent application describes a method for forming conductive features on a substrate using a Chemical Mechanical Polishing (CMP) process and an Interlayer Dielectric (ILD) layer.

A first conductive feature is formed on a substrate.
A via is created to connect with the first conductive feature, using a conductive material.
The top surface of the via is polished using a CMP process.
An ILD layer is deposited on the via.
A trench is formed within the ILD layer to expose the via.
The trench is filled with a second conductive feature that also connects with the via, using the same material as the conductive material.

Original Abstract Submitted

A method includes forming a first conductive feature on a substrate, forming a via that contacts the first conductive feature, the via comprising a conductive material, performing a Chemical Mechanical Polishing (CMP) process to a top surface of the via, depositing an Interlayer Dielectric (ILD) layer on the via, forming a trench within the ILD layer to expose the via, and filling the trench with a second conductive feature that contacts the via, the second conductive feature comprising a same material as the conductive material.