Category:Javier A. DeLaCruz of San Jose CA (US)

Javier A. DeLaCruz of San Jose CA (US)

Executive Summary

Javier A. DeLaCruz of San Jose CA (US) is an inventor who has filed 4 patents. Their primary areas of innovation include SEMICONDUCTOR DEVICES NOT COVERED BY CLASS (2 patents), SEMICONDUCTOR DEVICES NOT COVERED BY CLASS (2 patents), SEMICONDUCTOR DEVICES NOT COVERED BY CLASS (2 patents), and they have worked with companies such as ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC. (4 patents). Their most frequent collaborators include (3 collaborations), (2 collaborations), (1 collaborations).

Patent Filing Activity

Technology Areas

List of Technology Areas

• H01L24/08 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H01L23/573 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H01L24/05 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H01L24/48 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H01L24/83 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H01L23/5223 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L23/5226 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L23/5286 ({Geometry or} layout of the interconnection structure {(): 1 patents
• H01L23/5383 ({Multilayer substrates (): 1 patents
• H01L23/5389 (the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates ({): 1 patents
• H01L24/17 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L25/16 (the devices being of types provided for in two or more different main groups of groups): 1 patents
• H01L28/60 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2924/1205 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L24/06 ({of a plurality of bonding areas}): 1 patents
• G01R31/275 (MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits): 1 patents
• G01R31/2856 (Testing of electronic circuits, e.g. by signal tracer ({EMC, EMP or similar testing of electronic circuits): 1 patents
• H01L25/0657 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L24/94 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/04042 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/83896 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L22/34 ({Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line (switching, multiplexing, gating devices): 1 patents
• H01L23/528 ({Geometry or} layout of the interconnection structure {(): 1 patents
• H01L23/562 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L24/27 ({Manufacturing methods}): 1 patents
• H01L24/29 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L24/32 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L24/73 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L24/49 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/08237 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/29082 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/29187 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/32225 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/48091 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/48106 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/48225 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/49171 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/73215 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents

Companies

List of Companies

• ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.: 4 patents

Collaborators

• Belgacem Haba of Saratoga CA (US) (3 collaborations)
• Rajesh Katkar of Milpitas CA (US) (2 collaborations)
• Jung Ko of San Jose CA (US) (1 collaborations)