Category:Laura Wills Mirkarimi of Sunol CA (US)

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Laura Wills Mirkarimi of Sunol CA (US)

Executive Summary

Laura Wills Mirkarimi of Sunol CA (US) is an inventor who has filed 6 patents. Their primary areas of innovation include {Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected} (4 patents), SEMICONDUCTOR DEVICES NOT COVERED BY CLASS (4 patents), SEMICONDUCTOR DEVICES NOT COVERED BY CLASS (3 patents), and they have worked with companies such as ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC. (6 patents). Their most frequent collaborators include (5 collaborations), (5 collaborations), (4 collaborations).

Patent Filing Activity

Laura Wills Mirkarimi of Sunol CA (US) Monthly Patent Applications.png

Technology Areas

Laura Wills Mirkarimi of Sunol CA (US) Top Technology Areas.png

List of Technology Areas

  • H01L24/80 ({Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected}): 4 patents
  • H01L2224/80896 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 4 patents
  • H01L25/0657 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 3 patents
  • H01L24/08 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 3 patents
  • H01L2224/80895 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 3 patents
  • H01L2224/08145 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
  • H01L23/5226 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
  • H01L21/76898 ({formed through a semiconductor substrate}): 2 patents
  • H01L23/481 (Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements {; Selection of materials therefor}): 2 patents
  • H01L24/09 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
  • H01L21/561 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L23/3121 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L24/97 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L2224/0401 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L2924/3511 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L2924/35121 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L2224/80948 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L22/34 ({Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line (switching, multiplexing, gating devices): 1 patents
  • H01L21/7685 ({the layer covering a conductive structure (): 1 patents
  • H01L21/76877 ({Thin films associated with contacts of capacitors}): 1 patents
  • H01L23/53238 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L23/53266 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L23/5386 (the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates ({): 1 patents
  • H01L24/03 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L24/05 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L24/06 ({of a plurality of bonding areas}): 1 patents
  • H01L25/50 ({Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group): 1 patents
  • H01L24/94 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L2224/05147 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L2224/05181 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L2224/05184 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L2224/08146 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L2224/08057 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L2224/08147 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L21/76843 ({formed in openings in a dielectric}): 1 patents
  • H01L21/76895 (Applying interconnections to be used for carrying current between separate components within a device {comprising conductors and dielectrics}): 1 patents
  • H01L23/4824 (consisting of lead-in layers inseparably applied to the semiconductor body {(electrodes): 1 patents
  • H01L24/32 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L24/83 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L2225/06524 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
  • H01L2225/06544 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents

Companies

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List of Companies

  • ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.: 6 patents

Collaborators

Subcategories

This category has the following 10 subcategories, out of 10 total.

Pages in category "Laura Wills Mirkarimi of Sunol CA (US)"

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