Category:Cyprian Emeka Uzoh of San Jose CA (US)

Cyprian Emeka Uzoh of San Jose CA (US)

Executive Summary

Cyprian Emeka Uzoh of San Jose CA (US) is an inventor who has filed 18 patents. Their primary areas of innovation include {Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected} (10 patents), SEMICONDUCTOR DEVICES NOT COVERED BY CLASS (9 patents), SEMICONDUCTOR DEVICES NOT COVERED BY CLASS (9 patents), and they have worked with companies such as ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC. (16 patents), Adeia Semiconductor Bonding Technologies Inc. (2 patents). Their most frequent collaborators include (8 collaborations), (5 collaborations), (4 collaborations).

Patent Filing Activity

Technology Areas

List of Technology Areas

• H01L24/80 ({Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected}): 10 patents
• H01L24/08 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 9 patents
• H01L2224/80896 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 9 patents
• H01L2224/80895 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 8 patents
• H01L2224/08145 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 7 patents
• H01L25/0657 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 6 patents
• H01L24/05 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 5 patents
• H01L25/50 ({Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group): 5 patents
• H01L24/03 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 4 patents
• H01L2224/05647 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 3 patents
• H01L2224/80031 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 3 patents
• H01L2224/05147 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 3 patents
• H01L21/76898 ({formed through a semiconductor substrate}): 3 patents
• H01L2224/08225 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H01L2224/03462 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H01L2224/03616 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H01L2224/05082 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H01L2224/05166 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H01L2224/05181 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H01L2224/08146 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H01L21/561 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H01L23/3121 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H01L24/97 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H01L2924/3511 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H01L2224/80013 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H01L2224/80011 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H01L23/481 (Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements {; Selection of materials therefor}): 2 patents
• H01L24/09 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H01L24/94 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H01L2224/05184 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H01L23/5226 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H01L2224/80047 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/80365 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/80379 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2924/04642 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2924/0504 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2924/0544 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2924/059 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L23/562 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L23/053 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L23/3157 ({Partial encapsulation or coating (mask layer used as insulation layer): 1 patents
• H01L23/473 (by flowing liquids {(): 1 patents
• H01L2224/03464 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/0347 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/0362 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/0384 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/03845 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/05013 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/05015 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/05026 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/05076 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/05105 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/05109 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/05111 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/05144 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/05155 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/05171 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/05551 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/05554 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/05555 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/05576 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/05578 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/05605 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/05609 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/05611 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/05639 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/05644 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/05655 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/80375 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/0401 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2924/35121 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L21/304 (Mechanical treatment, e.g. grinding, polishing, cutting {(): 1 patents
• H01L21/306 (Chemical or electrical treatment, e.g. electrolytic etching (to form insulating layers): 1 patents
• H01L21/3081 (using masks (): 1 patents
• H01L21/683 (for supporting or gripping (for conveying): 1 patents
• H01L23/3135 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2225/06513 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2225/06541 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2924/1304 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2924/1434 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2924/1461 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2924/351 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2924/3512 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L21/67046 (Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components {; Apparatus not specifically provided for elsewhere (processes per se): 1 patents
• H01L21/67051 (Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components {; Apparatus not specifically provided for elsewhere (processes per se): 1 patents
• H01L21/67132 ({Apparatus for placing on an insulating substrate, e.g. tape}): 1 patents
• H01L21/67253 (Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components {; Apparatus not specifically provided for elsewhere (processes per se): 1 patents
• H01L23/48 (Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements {; Selection of materials therefor}): 1 patents
• H01L25/065 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L21/6836 ({Wafer tapes, e.g. grinding or dicing support tapes (adhesive tapes in general): 1 patents
• H01L21/6838 (for supporting or gripping (for conveying): 1 patents
• H01L21/78 (with subsequent division of the substrate into plural individual devices (cutting to change the surface-physical characteristics or shape of semiconductor bodies): 1 patents
• H01L21/67144 ({Apparatus for mounting on conductive members, e.g. leadframes or conductors on insulating substrates}): 1 patents
• H01L2224/81005 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L24/81 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/97 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/81801 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/80006 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2221/68322 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2221/68336 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2221/68363 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2221/68381 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/80012 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/80019 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L23/5384 ({Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors (): 1 patents
• H01L23/5385 (the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates ({): 1 patents
• H01L23/5386 (the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates ({): 1 patents
• H01L24/95 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L21/6835 ({using temporarily an auxiliary support}): 1 patents
• H01L2221/68309 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2221/68313 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2221/68354 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L25/0652 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L23/5381 (the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates ({): 1 patents
• H01L22/32 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2225/06572 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2225/06582 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2225/06596 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L24/06 ({of a plurality of bonding areas}): 1 patents
• H01L2224/08057 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/08147 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L21/76843 ({formed in openings in a dielectric}): 1 patents
• H01L21/76895 (Applying interconnections to be used for carrying current between separate components within a device {comprising conductors and dielectrics}): 1 patents
• H01L23/4824 (consisting of lead-in layers inseparably applied to the semiconductor body {(electrodes): 1 patents
• H01L24/32 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L24/83 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2225/06524 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2225/06544 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• B32B15/016 (all layers being exclusively metallic {(making layered metal workpieces by pressure cladding): 1 patents
• B32B3/266 ({characterised by an apertured layer, the apertures going through the whole thickness of the layer, e.g. expanded metal, perforated layer, slit layer regular cells): 1 patents
• B32B3/30 (characterised by a layer formed with recesses or projections, e.g. {hollows, grooves, protuberances, ribs (apertured layer): 1 patents
• B32B15/017 (all layers being exclusively metallic {(making layered metal workpieces by pressure cladding): 1 patents
• B32B15/20 (LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM): 1 patents
• B32B2250/02 (LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM): 1 patents
• B32B2307/202 (LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM): 1 patents
• B32B2307/206 (LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM): 1 patents
• B32B2311/22 (LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM): 1 patents
• B32B2311/24 (LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM): 1 patents
• H01L2224/0345 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/03614 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/05073 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/05124 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/05186 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/05571 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/05624 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/8002 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/80357 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/80906 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2224/94 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2924/04941 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L24/20 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L23/298 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L23/3178 ({Coating or filling in grooves made in the semiconductor body}): 1 patents

Companies

List of Companies

• ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.: 16 patents
• Adeia Semiconductor Bonding Technologies Inc.: 2 patents

Collaborators

• Rajesh Katkar of Milpitas CA (US) (8 collaborations)
• Belgacem Haba of Saratoga CA (US) (5 collaborations)
• Guilian Gao of San Jose CA (US) (4 collaborations)
• Laura Wills Mirkarimi of Sunol CA (US) (4 collaborations)
• Jeremy Alfred Theil of Mountain View CA (US) (4 collaborations)
• Thomas Workman of San Jose CA (US) (3 collaborations)
• Gaius Gillman Fountain, JR. of Youngsville NC (US) (3 collaborations)
• Bongsub Lee of Santa Clara CA (US) (3 collaborations)
• Guilian Gao of Campbell CA (US) (2 collaborations)
• Gabriel Z. Guevara of San Jose CA (US) (1 collaborations)
• Joy Watanabe of Campbell CA (US) (1 collaborations)
• Arkalgud R. Sitaram of Cupertino CA (US) (1 collaborations)
• Paul Enquist of Cary NC (US) (1 collaborations)
• Pawel Mrozek of San Jose CA (US) (1 collaborations)
• Aaron Todd Francis of San Jose CA (US) (1 collaborations)
• Gabriel Guevara of Gilroy CA (US) (1 collaborations)
• Dominik Suwito of San Jose CA (US) (1 collaborations)
• Oliver Zhao of Sunnyvale CA (US) (1 collaborations)
• Gaius Gillman Fountain, Jr. of Youngsville NC (US) (1 collaborations)