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==Patent applications for Advanced Micro Devices, Inc. on June 27th, 2024== | ==Patent applications for Advanced Micro Devices, Inc. on June 27th, 2024== | ||
Revision as of 08:51, 28 June 2024
Contents
- 1 Patent applications for Advanced Micro Devices, Inc. on June 27th, 2024
- 1.1 OVER-VOLTAGE TOLERANT POWER SUPPLY SENSING CIRCUIT WITH PROGRAMMABLE TRIP-POINT (18089057)
- 1.2 POWER-AWARE, HISTORY-BASED GRAPHICS POWER OPTIMIZATION (18146733)
- 1.3 RUNTIME-LEARNING GRAPHICS POWER OPTIMIZATION (18146776)
- 1.4 BUFFER DISPLAY DATA IN A CHIPLET ARCHITECTURE (18146811)
- 1.5 ACCELERATING RELAXED REMOTE ATOMICS ON MULTIPLE WRITER OPERATIONS (18087964)
- 1.6 Extended Training for Memory (18146538)
- 1.7 System Memory Training with Chipset Attached Memory (18146929)
- 1.8 PERFORMANCE OF BANK REFRESH (18086942)
- 1.9 PARTITION AND ISOLATION OF A PROCESSING-IN-MEMORY (PIM) DEVICE (18601006)
- 1.10 JOB SUBMISSION ALIGNMENT WITH WORLD SWITCH (18088955)
- 1.11 BUDGET-BASED TIME SLICE ASSIGNMENT FOR MULTIPLE VIRTUAL FUNCTIONS (18088962)
- 1.12 MULTI-LEVEL SCHEDULING FOR IMPROVED QUALITY OF SERVICE (18085902)
- 1.13 DEVICES, SYSTEMS, AND METHODS FOR INJECTING FABRICATED ERRORS INTO MACHINE CHECK ARCHITECTURES (18089135)
- 1.14 Leveraging Processing in Memory Registers as Victim Buffers (18146509)
- 1.15 DISTRIBUTED CACHING POLICY FOR LARGE-SCALE DEEP LEARNING TRAINING DATA PRE-PROCESSING (18089480)
- 1.16 Condensed Coherence Directory Entries for Processing-in-Memory (18146904)
- 1.17 Managing a Cache Using Per Memory Region Reuse Distance Estimation (18146883)
- 1.18 Physical Adjustment to System Memory with Chipset Attached Memory (18146920)
- 1.19 OPTIMIZING LOW PRECISION AND SPARSITY INFERENCE WITHOUT RETRAINING (18146828)
- 1.20 TRAVERSING MULTIPLE REGIONS OF A BOUNDING VOLUME HIERARCHY IN PARALLEL (18089442)
- 1.21 Memory Verification Using Processing-in-Memory (18146558)
- 1.22 THROUGH-MAGNETIC INDUCTOR (18478416)
- 1.23 LOOKUP TABLE OPTIMIZATION FOR HIGH SPEED TRANSMIT FEED-FORWARD EQUALIZATION LINK (18086960)
Patent applications for Advanced Micro Devices, Inc. on June 27th, 2024
OVER-VOLTAGE TOLERANT POWER SUPPLY SENSING CIRCUIT WITH PROGRAMMABLE TRIP-POINT (18089057)
Main Inventor
Thanapandi Ganesan
POWER-AWARE, HISTORY-BASED GRAPHICS POWER OPTIMIZATION (18146733)
Main Inventor
Tzyy-Juin Kao
RUNTIME-LEARNING GRAPHICS POWER OPTIMIZATION (18146776)
Main Inventor
Rashad Oreifej
BUFFER DISPLAY DATA IN A CHIPLET ARCHITECTURE (18146811)
Main Inventor
Gia Tung Phan
ACCELERATING RELAXED REMOTE ATOMICS ON MULTIPLE WRITER OPERATIONS (18087964)
Main Inventor
John Kalamatianos
Extended Training for Memory (18146538)
Main Inventor
Alicia Wen Ju Yurie Leong
System Memory Training with Chipset Attached Memory (18146929)
Main Inventor
Jerry Anton Ahrens
PERFORMANCE OF BANK REFRESH (18086942)
Main Inventor
Kedarnath Balakrishnan
PARTITION AND ISOLATION OF A PROCESSING-IN-MEMORY (PIM) DEVICE (18601006)
Main Inventor
SOORAJ PUTHOOR
JOB SUBMISSION ALIGNMENT WITH WORLD SWITCH (18088955)
Main Inventor
Yuping Shen
BUDGET-BASED TIME SLICE ASSIGNMENT FOR MULTIPLE VIRTUAL FUNCTIONS (18088962)
Main Inventor
Yuping Shen
MULTI-LEVEL SCHEDULING FOR IMPROVED QUALITY OF SERVICE (18085902)
Main Inventor
Ahmed M. Abdelkhalek
DEVICES, SYSTEMS, AND METHODS FOR INJECTING FABRICATED ERRORS INTO MACHINE CHECK ARCHITECTURES (18089135)
Main Inventor
Vilas Sridharan
Leveraging Processing in Memory Registers as Victim Buffers (18146509)
Main Inventor
Jagadish B Kotra
DISTRIBUTED CACHING POLICY FOR LARGE-SCALE DEEP LEARNING TRAINING DATA PRE-PROCESSING (18089480)
Main Inventor
Kishore Punniyamurthy
Condensed Coherence Directory Entries for Processing-in-Memory (18146904)
Main Inventor
Travis Henry Boraten
Managing a Cache Using Per Memory Region Reuse Distance Estimation (18146883)
Main Inventor
John Kalamatianos
Physical Adjustment to System Memory with Chipset Attached Memory (18146920)
Main Inventor
Jerry Anton Ahrens
OPTIMIZING LOW PRECISION AND SPARSITY INFERENCE WITHOUT RETRAINING (18146828)
Main Inventor
Adam H. Li
TRAVERSING MULTIPLE REGIONS OF A BOUNDING VOLUME HIERARCHY IN PARALLEL (18089442)
Main Inventor
David William John Pankratz
Memory Verification Using Processing-in-Memory (18146558)
Main Inventor
Robin Conradine Knauerhase
THROUGH-MAGNETIC INDUCTOR (18478416)
Main Inventor
Robert Grant Spurney
LOOKUP TABLE OPTIMIZATION FOR HIGH SPEED TRANSMIT FEED-FORWARD EQUALIZATION LINK (18086960)
Main Inventor
Pradeep Jayaraman