Chee-Wee LIU

Executive Summary

Chee-Wee LIU is an inventor who has filed 10 patents. Their primary areas of innovation include SEMICONDUCTOR DEVICES NOT COVERED BY CLASS (4 patents), SEMICONDUCTOR DEVICES NOT COVERED BY CLASS (3 patents), SEMICONDUCTOR DEVICES NOT COVERED BY CLASS (3 patents), and they have worked with companies such as TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. (8 patents), Taiwan Semiconductor Manufacturing Company, Ltd. (2 patents). Their most frequent collaborators include (5 collaborations), (3 collaborations), (2 collaborations).

Patent Filing Activity

Technology Areas

List of Technology Areas

• H01L29/42392 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 4 patents
• H01L29/0673 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 3 patents
• H01L29/66439 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 3 patents
• H10D64/017 (No explanation available): 3 patents
• H01L29/78696 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 3 patents
• H01L21/823807 (to produce devices, e.g. integrated circuits, each consisting of a plurality of components): 2 patents
• H01L21/823828 (to produce devices, e.g. integrated circuits, each consisting of a plurality of components): 2 patents
• H01L29/66545 ({using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate}): 2 patents
• G11C11/419 (forming {static} cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger): 2 patents
• H10B10/12 (ELECTRONIC MEMORY DEVICES): 2 patents
• H10D30/014 (No explanation available): 2 patents
• H10D30/43 (No explanation available): 2 patents
• H10D30/6735 (No explanation available): 2 patents
• H10D62/121 (No explanation available): 2 patents
• H10D84/0167 (No explanation available): 2 patents
• H10D84/017 (No explanation available): 2 patents
• H10D84/0186 (No explanation available): 2 patents
• H10D84/038 (No explanation available): 2 patents
• H01L27/092 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H01L29/775 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H01L29/6684 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L29/516 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L29/78391 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L21/8221 ({Three dimensional integrated circuits stacked in different levels}): 1 patents
• H01L21/761 (Making of isolation regions between components): 1 patents
• H01L21/823814 (to produce devices, e.g. integrated circuits, each consisting of a plurality of components): 1 patents
• H01L21/823878 (to produce devices, e.g. integrated circuits, each consisting of a plurality of components): 1 patents
• H01L27/0688 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L27/0922 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L27/1207 ({combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits}): 1 patents
• H01L29/7848 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L23/481 (Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements {; Selection of materials therefor}): 1 patents
• H10D30/024 (No explanation available): 1 patents
• H10D30/6211 (No explanation available): 1 patents
• H10D30/6219 (No explanation available): 1 patents
• H10D84/856 (No explanation available): 1 patents
• H01L21/76805 ({the opening being a via or contact hole penetrating the underlying conductor}): 1 patents
• H01L21/7684 (Applying interconnections to be used for carrying current between separate components within a device {comprising conductors and dielectrics}): 1 patents
• H01L21/76886 ({Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances}): 1 patents
• H01L21/76895 (Applying interconnections to be used for carrying current between separate components within a device {comprising conductors and dielectrics}): 1 patents
• H10D88/01 (No explanation available): 1 patents
• H01L21/02697 ({Forming conducting materials on a substrate}): 1 patents
• H01L21/02112 ({characterised by the material of the layer}): 1 patents
• H01L21/02263 ({deposition from the gas or vapour phase}): 1 patents
• H01L21/47 (Organic layers, e.g. photoresist (): 1 patents
• H01L23/5286 ({Geometry or} layout of the interconnection structure {(): 1 patents
• H10D62/151 (No explanation available): 1 patents
• H10D84/0188 (No explanation available): 1 patents
• H10D84/85 (No explanation available): 1 patents
• H01L21/823871 (to produce devices, e.g. integrated circuits, each consisting of a plurality of components): 1 patents
• H01L29/78693 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L29/161 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L29/401 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L29/66742 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents

Companies

List of Companies

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.: 8 patents
• Taiwan Semiconductor Manufacturing Company, Ltd.: 2 patents

Collaborators

• Hsin-Cheng LIN (5 collaborations)
• Tao CHOU (3 collaborations)
• Chien-Te TU (2 collaborations)
• Kuan-Ying CHIU (2 collaborations)
• Jih-Chao CHIU (2 collaborations)
• Yu-Rui CHEN (1 collaborations)
• Zefu ZHAO (1 collaborations)
• Yun-Wen CHEN (1 collaborations)
• Yi-Chun LIU (1 collaborations)
• Chun-Yi CHENG (1 collaborations)
• Chien-Te Tu (1 collaborations)
• Chia-Che CHUNG (1 collaborations)
• Chia-Jung TSEN (1 collaborations)
• Ching-Wang YAO (1 collaborations)
• Li-Kai WANG (1 collaborations)
• Chenming HU of Oakland CA (US) (1 collaborations)
• Yuan-Ming LIU (1 collaborations)
• Eknath SARKAR (1 collaborations)
• Shahaji B. MORE (1 collaborations)
• Cheng-Han LEE (1 collaborations)
• Chung-En TSAI (1 collaborations)
• Shih-Ya LIN (1 collaborations)
• Shih-Chieh CHANG (1 collaborations)