Nvidia corporation (20250015966). TWO-WAY TRANSCEIVER ENCODING FOR SIMULTANEOUS BIDIRECTIONAL SIGNALING: Difference between revisions
Creating a new page |
Creating a new page |
||
Line 11: | Line 11: | ||
==Inventor(s)== | ==Inventor(s)== | ||
[[:Category:Ofek Abadi of Nahariya | [[:Category:Ofek Abadi of Nahariya IL|Ofek Abadi of Nahariya IL]][[Category:Ofek Abadi of Nahariya IL]] | ||
==TWO-WAY TRANSCEIVER ENCODING FOR SIMULTANEOUS BIDIRECTIONAL SIGNALING== | ==TWO-WAY TRANSCEIVER ENCODING FOR SIMULTANEOUS BIDIRECTIONAL SIGNALING== | ||
Line 17: | Line 17: | ||
This abstract first appeared for US patent application 20250015966 titled 'TWO-WAY TRANSCEIVER ENCODING FOR SIMULTANEOUS BIDIRECTIONAL SIGNALING | This abstract first appeared for US patent application 20250015966 titled 'TWO-WAY TRANSCEIVER ENCODING FOR SIMULTANEOUS BIDIRECTIONAL SIGNALING | ||
==Original Abstract Submitted== | ==Original Abstract Submitted== |
Latest revision as of 08:25, 25 March 2025
TWO-WAY TRANSCEIVER ENCODING FOR SIMULTANEOUS BIDIRECTIONAL SIGNALING
Organization Name
Inventor(s)
TWO-WAY TRANSCEIVER ENCODING FOR SIMULTANEOUS BIDIRECTIONAL SIGNALING
This abstract first appeared for US patent application 20250015966 titled 'TWO-WAY TRANSCEIVER ENCODING FOR SIMULTANEOUS BIDIRECTIONAL SIGNALING
Original Abstract Submitted
a system includes a series of first/second transceivers mutually coupled over data lanes as bidirectional transceivers, and first/second control logic coupled to the first/second transceivers, respectively. an encoding of bit inversions by the first/second control logic causes: first pair of transceivers coupled over a first data lane to transmit non-inverted bits in a first direction and a second direction over the first data lane; second pair of transceivers coupled over a second data lane to transmit inverted bits in a first direction but not a second direction over the second data lane; third pair of transceivers coupled over a third data lane to transmit inverted bits in the second direction but not the first direction over the third data lane; and fourth pair of transceivers coupled over a fourth data lane to transmit inverted bits in the first direction and the second direction over the fourth data lane.