Apple inc. (20250094174). Coprocessor Prefetcher: Difference between revisions
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==Inventor(s)== | ==Inventor(s)== | ||
[[:Category:Brandon H. Dwiel of Boston MA | [[:Category:Brandon H. Dwiel of Boston MA US|Brandon H. Dwiel of Boston MA US]][[Category:Brandon H. Dwiel of Boston MA US]] | ||
[[:Category:Andrew J. Beaumont-smith of Cambridge MA | [[:Category:Andrew J. Beaumont-smith of Cambridge MA US|Andrew J. Beaumont-smith of Cambridge MA US]][[Category:Andrew J. Beaumont-smith of Cambridge MA US]] | ||
[[:Category:Eric J. Furbish of Austin TX | [[:Category:Eric J. Furbish of Austin TX US|Eric J. Furbish of Austin TX US]][[Category:Eric J. Furbish of Austin TX US]] | ||
[[:Category:John D. Pape of Cedar Park TX | [[:Category:John D. Pape of Cedar Park TX US|John D. Pape of Cedar Park TX US]][[Category:John D. Pape of Cedar Park TX US]] | ||
[[:Category:Stephen G. Meier of Los Altos CA | [[:Category:Stephen G. Meier of Los Altos CA US|Stephen G. Meier of Los Altos CA US]][[Category:Stephen G. Meier of Los Altos CA US]] | ||
[[:Category:Tyler J. Huberty of Sunnyvale CA | [[:Category:Tyler J. Huberty of Sunnyvale CA US|Tyler J. Huberty of Sunnyvale CA US]][[Category:Tyler J. Huberty of Sunnyvale CA US]] | ||
==Coprocessor Prefetcher== | ==Coprocessor Prefetcher== |
Latest revision as of 17:52, 22 March 2025
Coprocessor Prefetcher
Organization Name
Inventor(s)
Brandon H. Dwiel of Boston MA US
Andrew J. Beaumont-smith of Cambridge MA US
Eric J. Furbish of Austin TX US
John D. Pape of Cedar Park TX US
Stephen G. Meier of Los Altos CA US
Tyler J. Huberty of Sunnyvale CA US
Coprocessor Prefetcher
This abstract first appeared for US patent application 20250094174 titled 'Coprocessor Prefetcher
Original Abstract Submitted
a prefetcher for a coprocessor is disclosed. an apparatus includes a processor and a coprocessor that are configured to execute processor and coprocessor instructions, respectively. the processor and coprocessor instructions appear together in code sequences fetched by the processor, with the coprocessor instructions being provided to the coprocessor by the processor. the apparatus further includes a coprocessor prefetcher configured to monitor a code sequence fetched by the processor and, in response to identifying a presence of coprocessor instructions in the code sequence, capture the memory addresses, generated by the processor, of operand data for coprocessor instructions. the coprocessor is further configured to issue, for a cache memory accessible to the coprocessor, prefetches for data associated with the memory addresses prior to execution of the coprocessor instructions by the coprocessor.
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