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Apple inc. (20250093932). MEMORY HIERARCHY POWER MANAGEMENT: Difference between revisions

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==Inventor(s)==
==Inventor(s)==


[[:Category:John G. Dorsey of San Francisco CA (US)|John G. Dorsey of San Francisco CA (US)]][[Category:John G. Dorsey of San Francisco CA (US)]]
[[:Category:John G. Dorsey of San Francisco CA US|John G. Dorsey of San Francisco CA US]][[Category:John G. Dorsey of San Francisco CA US]]


[[:Category:Bryan R. Hinch of Campbell CA (US)|Bryan R. Hinch of Campbell CA (US)]][[Category:Bryan R. Hinch of Campbell CA (US)]]
[[:Category:Bryan R. Hinch of Campbell CA US|Bryan R. Hinch of Campbell CA US]][[Category:Bryan R. Hinch of Campbell CA US]]


[[:Category:Ronit Banerjee of Mountain View CA (US)|Ronit Banerjee of Mountain View CA (US)]][[Category:Ronit Banerjee of Mountain View CA (US)]]
[[:Category:Ronit Banerjee of Mountain View CA US|Ronit Banerjee of Mountain View CA US]][[Category:Ronit Banerjee of Mountain View CA US]]


[[:Category:Karthic A. Palaniappan of Cupertino CA (US)|Karthic A. Palaniappan of Cupertino CA (US)]][[Category:Karthic A. Palaniappan of Cupertino CA (US)]]
[[:Category:Karthic A. Palaniappan of Cupertino CA US|Karthic A. Palaniappan of Cupertino CA US]][[Category:Karthic A. Palaniappan of Cupertino CA US]]


==MEMORY HIERARCHY POWER MANAGEMENT==
==MEMORY HIERARCHY POWER MANAGEMENT==

Latest revision as of 17:50, 22 March 2025

MEMORY HIERARCHY POWER MANAGEMENT

Organization Name

apple inc.

Inventor(s)

John G. Dorsey of San Francisco CA US

Bryan R. Hinch of Campbell CA US

Ronit Banerjee of Mountain View CA US

Karthic A. Palaniappan of Cupertino CA US

MEMORY HIERARCHY POWER MANAGEMENT

This abstract first appeared for US patent application 20250093932 titled 'MEMORY HIERARCHY POWER MANAGEMENT

Original Abstract Submitted

some embodiments include a system, apparatus, method, and computer program product for memory hierarchy power management. some embodiments include a performance controller that balances memory hierarchy power and compute power to maintain package-level power efficiency of a systems-on-a-chip (soc)-memory package. the performance controller can determine a ratio of memory hierarchy power to compute agent power, compare the ratio against a threshold value, and based on the comparison, determine how to manage memory hierarchy power. when the energy costs of the memory hierarchy power are large relative to the energy costs of the compute agent power, some embodiments include changing a performance state of a fabric and/or memory to increase the power efficiency of the overall soc-memory package, even though a number of memory stall cycles experienced by the compute agent may increase.

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