Samsung electronics co., ltd. (20250079320). SEMICONDUCTOR PACKAGES: Difference between revisions
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==Inventor(s)== | |||
[[:Category:Junghoon Kang of Suwon-si (KR)|Junghoon Kang of Suwon-si (KR)]][[Category:Junghoon Kang of Suwon-si (KR)]] | |||
==SEMICONDUCTOR PACKAGES== | |||
This abstract first appeared for US patent application 20250079320 titled 'SEMICONDUCTOR PACKAGES | |||
==Original Abstract Submitted== | |||
a semiconductor package comprising: a first redistribution substrate; a module structure on the first redistribution substrate; a first molding layer on the first redistribution substrate and extending around the module structure; a second redistribution substrate on the module structure and the first molding layer; and a first vertical connection structure on a side of the module structure and electrically connecting the first redistribution substrate and the second redistribution substrate, wherein the module structure includes: a third redistribution substrate; a fourth redistribution substrate on the third redistribution substrate; a first semiconductor chip between the third redistribution substrate and the fourth redistribution substrate; a second molding layer between the third redistribution substrate and the fourth redistribution substrate and extending around the first semiconductor chip; and a second semiconductor chip on the fourth redistribution substrate, wherein the first semiconductor chip and the second semiconductor chip are electrically connected by the fourth redistribution substrate. | |||
[[Category:H01L23/538]] | |||
[[Category:H01L23/00]] | |||
[[Category:H01L23/31]] | |||
[[Category:H01L23/48]] | |||
[[Category:H01L23/498]] | |||
[[Category:H01L25/065]] | |||
[[Category:H01L25/10]] | |||
[[Category:CPC_H01L23/5385]] |
Latest revision as of 02:10, 17 March 2025
SEMICONDUCTOR PACKAGES
Organization Name
Inventor(s)
Junghoon Kang of Suwon-si (KR)
SEMICONDUCTOR PACKAGES
This abstract first appeared for US patent application 20250079320 titled 'SEMICONDUCTOR PACKAGES
Original Abstract Submitted
a semiconductor package comprising: a first redistribution substrate; a module structure on the first redistribution substrate; a first molding layer on the first redistribution substrate and extending around the module structure; a second redistribution substrate on the module structure and the first molding layer; and a first vertical connection structure on a side of the module structure and electrically connecting the first redistribution substrate and the second redistribution substrate, wherein the module structure includes: a third redistribution substrate; a fourth redistribution substrate on the third redistribution substrate; a first semiconductor chip between the third redistribution substrate and the fourth redistribution substrate; a second molding layer between the third redistribution substrate and the fourth redistribution substrate and extending around the first semiconductor chip; and a second semiconductor chip on the fourth redistribution substrate, wherein the first semiconductor chip and the second semiconductor chip are electrically connected by the fourth redistribution substrate.