Difference between revisions of "Category:Chih-Hao WANG"

Chih-Hao WANG

Executive Summary

Chih-Hao WANG is an inventor who has filed 11 patents. Their primary areas of innovation include {using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate} (5 patents), SEMICONDUCTOR DEVICES NOT COVERED BY CLASS (4 patents), SEMICONDUCTOR DEVICES NOT COVERED BY CLASS (4 patents), and they have worked with companies such as Taiwan Semiconductor Manufacturing Co., Ltd. (7 patents), TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. (4 patents). Their most frequent collaborators include (5 collaborations), (3 collaborations), (3 collaborations).

Patent Filing Activity

Technology Areas

List of Technology Areas

• H01L29/66545 ({using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate}): 5 patents
• H01L29/78696 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 4 patents
• H01L27/0886 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 4 patents
• H01L29/66795 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 4 patents
• H01L29/775 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 3 patents
• H01L29/66439 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 3 patents
• H01L29/42392 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 3 patents
• H01L21/823878 (to produce devices, e.g. integrated circuits, each consisting of a plurality of components): 3 patents
• H01L29/41791 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 3 patents
• H01L29/401 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 3 patents
• H01L21/823431 (to produce devices, e.g. integrated circuits, each consisting of a plurality of components): 3 patents
• H01L29/0673 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H01L21/823871 (to produce devices, e.g. integrated circuits, each consisting of a plurality of components): 2 patents
• H01L23/5226 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H01L29/0665 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H01L29/785 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H01L21/0228 ({deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD}): 2 patents
• H01L21/31111 ({by chemical means}): 2 patents
• H01L27/0924 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H01L29/0847 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H01L29/7851 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H01L29/66636 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 2 patents
• H01L21/76224 ({using trench refilling with dielectric materials (trench filling with polycristalline silicon): 2 patents
• H01L21/823418 (to produce devices, e.g. integrated circuits, each consisting of a plurality of components): 2 patents
• H01L27/092 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L21/823807 (to produce devices, e.g. integrated circuits, each consisting of a plurality of components): 1 patents
• H01L21/76232 (Dielectric regions {, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers}): 1 patents
• H01L21/764 (Making of isolation regions between components): 1 patents
• H01L21/7682 (Applying interconnections to be used for carrying current between separate components within a device {comprising conductors and dielectrics}): 1 patents
• H01L21/76843 ({formed in openings in a dielectric}): 1 patents
• H01L21/823821 (to produce devices, e.g. integrated circuits, each consisting of a plurality of components): 1 patents
• H01L27/0883 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L21/823412 (to produce devices, e.g. integrated circuits, each consisting of a plurality of components): 1 patents
• H01L21/823462 (to produce devices, e.g. integrated circuits, each consisting of a plurality of components): 1 patents
• H01L29/0649 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L2029/7858 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L29/41725 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L21/76802 (Applying interconnections to be used for carrying current between separate components within a device {comprising conductors and dielectrics}): 1 patents
• H01L21/76877 ({Thin films associated with contacts of capacitors}): 1 patents
• H01L21/28556 (from a gas or vapour, e.g. condensation): 1 patents
• H01L21/32137 ({of silicon-containing layers}): 1 patents
• H01L21/76898 ({formed through a semiconductor substrate}): 1 patents
• H01L23/481 (Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements {; Selection of materials therefor}): 1 patents
• H01L29/41733 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L29/66742 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L21/76871 ({Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers}): 1 patents
• H01L29/6656 ({using self aligned silicidation, i.e. salicide (formation of conductive layers comprising silicides): 1 patents
• H01L29/517 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L21/31116 ({by dry-etching}): 1 patents
• H01L21/823437 (to produce devices, e.g. integrated circuits, each consisting of a plurality of components): 1 patents
• H01L21/823481 (to produce devices, e.g. integrated circuits, each consisting of a plurality of components): 1 patents
• H01L27/0207 ({Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique}): 1 patents
• H01L29/7848 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L21/0217 ({the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz (): 1 patents
• H01L21/02271 ({deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition (): 1 patents
• H01L21/0274 (Making masks on semiconductor bodies for further photolithographic processing not provided for in group): 1 patents
• H01L21/0332 (comprising inorganic layers): 1 patents
• H01L21/31053 ({involving a dielectric removal step}): 1 patents
• H01L21/32139 ({using masks}): 1 patents
• H01L29/165 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L29/205 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L21/76897 ({Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step (self-aligned silicidation on field effect transistors): 1 patents
• H01L21/823468 (to produce devices, e.g. integrated circuits, each consisting of a plurality of components): 1 patents
• H01L21/823475 (to produce devices, e.g. integrated circuits, each consisting of a plurality of components): 1 patents
• H01L23/5283 ({Geometry or} layout of the interconnection structure {(): 1 patents
• H01L23/5286 ({Geometry or} layout of the interconnection structure {(): 1 patents
• H01L29/4175 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
• H01L29/6681 (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents

Companies

List of Companies

• Taiwan Semiconductor Manufacturing Co., Ltd.: 7 patents
• TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.: 4 patents

Collaborators

• Kuo-Cheng CHIANG (5 collaborations)
• Lung-Kun CHU (3 collaborations)
• Jia-Ni YU (3 collaborations)
• Mao-Lin HUANG (3 collaborations)
• Kuan-Lun CHENG (3 collaborations)
• Chun-Fu LU (2 collaborations)
• Chung-Wei HSU (2 collaborations)
• Kuo-Cheng CHING (2 collaborations)
• Ching-Wei TSAI (2 collaborations)
• Chia-Hao CHANG (2 collaborations)
• Yu-Ming LIN (2 collaborations)
• Shi Ning JU (2 collaborations)
• Shih-Cheng CHEN (1 collaborations)
• Chun-Hsiung LIN (1 collaborations)
• Li-Zhen YU (1 collaborations)
• Cheng-Chi CHUANG (1 collaborations)
• Chun-Yuan CHEN (1 collaborations)
• Huan-Chieh SU (1 collaborations)
• Shang-Wen CHANG (1 collaborations)
• Yi-Hsun CHIU (1 collaborations)
• Shih-Chuan CHIU (1 collaborations)
• Tien-Lu LIN (1 collaborations)
• Jia-Chuan YOU (1 collaborations)
• Kuan-Ting PAN (1 collaborations)
• Shi-Ning JU (1 collaborations)