Samsung electronics co., ltd. (20250006641). SEMICONDUCTOR DEVICE: Difference between revisions
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==Inventor(s)== | ==Inventor(s)== | ||
[[:Category:Yoon Hee Kang of Suwon-si | [[:Category:Yoon Hee Kang of Suwon-si KR|Yoon Hee Kang of Suwon-si KR]][[Category:Yoon Hee Kang of Suwon-si KR]] | ||
[[:Category:Jong Min Baek of Suwon-si | [[:Category:Jong Min Baek of Suwon-si KR|Jong Min Baek of Suwon-si KR]][[Category:Jong Min Baek of Suwon-si KR]] | ||
[[:Category:Eui Bok Lee of Suwon-si | [[:Category:Eui Bok Lee of Suwon-si KR|Eui Bok Lee of Suwon-si KR]][[Category:Eui Bok Lee of Suwon-si KR]] | ||
==SEMICONDUCTOR DEVICE== | ==SEMICONDUCTOR DEVICE== | ||
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This abstract first appeared for US patent application 20250006641 titled 'SEMICONDUCTOR DEVICE | This abstract first appeared for US patent application 20250006641 titled 'SEMICONDUCTOR DEVICE | ||
==Original Abstract Submitted== | ==Original Abstract Submitted== |
Latest revision as of 02:49, 25 March 2025
SEMICONDUCTOR DEVICE
Organization Name
Inventor(s)
SEMICONDUCTOR DEVICE
This abstract first appeared for US patent application 20250006641 titled 'SEMICONDUCTOR DEVICE
Original Abstract Submitted
a semiconductor device including a first interlayer insulating layer on a substrate, a lower wiring pattern in the first interlayer insulating layer, a second interlayer insulating layer on the first interlayer insulating layer, a via filling layer filling a via trench in the second interlayer insulating layer, a third interlayer insulating layer contacting an upper surface of the second interlayer insulating layer, and an upper wiring pattern in an upper wiring trench formed on the via trench in the third interlayer insulating layer and contacting an upper surface of the via filling layer, the upper wiring pattern including a first upper wiring barrier layer on sidewalls of the upper wiring trench, a second upper wiring barrier layer on sidewalls of the first upper wiring barrier layer and the upper surface of the via filling layer, and an upper wiring filling layer on the second upper wiring barrier layer.