Difference between revisions of "Taiwan Semiconductor Manufacturing Company, Ltd. patent applications published on November 30th, 2023"
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==Patent applications for Taiwan Semiconductor Manufacturing Company, Ltd. on November 30th, 2023== | ==Patent applications for Taiwan Semiconductor Manufacturing Company, Ltd. on November 30th, 2023== | ||
+ | |||
+ | ===PARTICLE REMOVER AND METHOD ([[US Patent Application 18448963. PARTICLE REMOVER AND METHOD simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18448963]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Wen-Hao Cheng | ||
+ | |||
+ | |||
+ | ===TRANSDUCER DEVICE AND METHOD OF MANUFACTURE ([[US Patent Application 17752558. TRANSDUCER DEVICE AND METHOD OF MANUFACTURE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17752558]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Chi-Yuan Shih | ||
+ | |||
+ | |||
+ | ===DEVICE FOR FORMING CONDUCTIVE POWDER ([[US Patent Application 18447161. DEVICE FOR FORMING CONDUCTIVE POWDER simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447161]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | You-Hua CHOU | ||
+ | |||
+ | |||
+ | ===POLISHING METROLOGY ([[US Patent Application 17898163. POLISHING METROLOGY simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17898163]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Chih Hung CHEN | ||
+ | |||
+ | |||
+ | ===CHEMICAL MECHANICAL POLISHING APPARATUS AND METHOD ([[US Patent Application 18446842. CHEMICAL MECHANICAL POLISHING APPARATUS AND METHOD simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446842]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Chun-Hsi Huang | ||
+ | |||
+ | |||
+ | ===SYSTEM AND METHOD FOR REMOVING DEBRIS DURING CHEMICAL MECHANICAL PLANARIZATION ([[US Patent Application 18447211. SYSTEM AND METHOD FOR REMOVING DEBRIS DURING CHEMICAL MECHANICAL PLANARIZATION simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447211]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Chun-Wei HSU | ||
+ | |||
+ | |||
+ | ===MICROELECTROMECHANICAL SYSTEMS DEVICE HAVING A MECHANICALLY ROBUST ANTI-STICTION/OUTGASSING STRUCTURE ([[US Patent Application 18364702. MICROELECTROMECHANICAL SYSTEMS DEVICE HAVING A MECHANICALLY ROBUST ANTI-STICTION/OUTGASSING STRUCTURE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18364702]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Kuei-Sung Chang | ||
+ | |||
+ | |||
+ | ===MEMS MICROPHONE AND MEMS ACCELEROMETER ON A SINGLE SUBSTRATE ([[US Patent Application 18446741. MEMS MICROPHONE AND MEMS ACCELEROMETER ON A SINGLE SUBSTRATE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446741]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Chun-Wen Cheng | ||
+ | |||
+ | |||
+ | ===WIRE-BOND DAMPER FOR SHOCK ABSORPTION ([[US Patent Application 18446740. WIRE-BOND DAMPER FOR SHOCK ABSORPTION simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446740]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Tsung-Lin Hsieh | ||
+ | |||
+ | |||
+ | ===DIELECTRIC PROTECTION LAYER CONFIGURED TO INCREASE PERFORMANCE OF MEMS DEVICE ([[US Patent Application 17825225. DIELECTRIC PROTECTION LAYER CONFIGURED TO INCREASE PERFORMANCE OF MEMS DEVICE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17825225]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Wen-Chuan Tai | ||
+ | |||
+ | |||
+ | ===SHUTTER DISC FOR A SEMICONDUCTOR PROCESSING TOOL ([[US Patent Application 18447543. SHUTTER DISC FOR A SEMICONDUCTOR PROCESSING TOOL simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447543]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Yi-Lin WANG | ||
+ | |||
+ | |||
+ | ===STRUCTURES AND METHODS FOR PROCESSING A SEMICONDUCTOR SUBSTRATE ([[US Patent Application 18446392. STRUCTURES AND METHODS FOR PROCESSING A SEMICONDUCTOR SUBSTRATE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446392]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Ming-Yi SHEN | ||
+ | |||
+ | |||
+ | ===DEPOSITION SYSTEM AND METHOD ([[US Patent Application 18447911. DEPOSITION SYSTEM AND METHOD simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447911]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Wen-Hao CHENG | ||
+ | |||
+ | |||
+ | ===Apparatus and Method for Use with a Substrate Chamber ([[US Patent Application 18447493. Apparatus and Method for Use with a Substrate Chamber simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447493]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Li-Ting Wang | ||
+ | |||
+ | |||
+ | ===APPARATUS FOR STORING AND TRANSPORTING SEMICONDUCTOR ELEMENTS, AND METHOD OF MAKING THE SAME ([[US Patent Application 18231763. APPARATUS FOR STORING AND TRANSPORTING SEMICONDUCTOR ELEMENTS, AND METHOD OF MAKING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18231763]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Tse-Lun HSU | ||
+ | |||
+ | |||
+ | ===WAFER DRYING SYSTEM ([[US Patent Application 18446858. WAFER DRYING SYSTEM simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446858]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Wei-Chun Hsu | ||
+ | |||
+ | |||
+ | ===TEMPERATURE SENSOR CIRCUITS AND CONTROL CIRCUITS AND METHOD FOR TEMPERATURE SENSOR CIRCUITS ([[US Patent Application 18150772. TEMPERATURE SENSOR CIRCUITS AND CONTROL CIRCUITS AND METHOD FOR TEMPERATURE SENSOR CIRCUITS simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18150772]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Jaw-Juinn HORNG | ||
+ | |||
+ | |||
+ | ===TEMPERATURE SENSING BASED ON METAL RAILS WITH DIFFERENT THERMAL-RESISTANCE COEFFICIENTS ([[US Patent Application 18170401. TEMPERATURE SENSING BASED ON METAL RAILS WITH DIFFERENT THERMAL-RESISTANCE COEFFICIENTS simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18170401]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Szu-Lin Liu | ||
+ | |||
+ | |||
+ | ===CAPACITOR-BASED TEMPERATURE-SENSING DEVICE ([[US Patent Application 18232329. CAPACITOR-BASED TEMPERATURE-SENSING DEVICE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18232329]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Shih-Lien Linus LU | ||
+ | |||
+ | |||
+ | ===ON-LINE ANALYSIS SYSTEM AND METHOD FOR SPECIALTY GASSES ([[US Patent Application 17752730. ON-LINE ANALYSIS SYSTEM AND METHOD FOR SPECIALTY GASSES simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17752730]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Chiang Jeh CHEN | ||
+ | |||
+ | |||
+ | ===IN-SITU APPARATUS FOR DETECTING ABNORMALITY IN PROCESS TUBE ([[US Patent Application 18361777. IN-SITU APPARATUS FOR DETECTING ABNORMALITY IN PROCESS TUBE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18361777]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Yu-Jen YANG | ||
+ | |||
+ | |||
+ | ===INTEGRATED BIOLOGICAL SENSING PLATFORM ([[US Patent Application 18232318. INTEGRATED BIOLOGICAL SENSING PLATFORM simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18232318]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Tsung-Tsun CHEN | ||
+ | |||
+ | |||
+ | ===On-Chip Heater ([[US Patent Application 18232719. On-Chip Heater simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18232719]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Tung-Tsun Chen | ||
+ | |||
+ | |||
+ | ===STRUCTURE AND PROCESS FOR PHOTONIC PACKAGES ([[US Patent Application 18366758. STRUCTURE AND PROCESS FOR PHOTONIC PACKAGES simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18366758]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Chen-Hua Yu | ||
+ | |||
+ | |||
+ | ===PACKAGED DEVICE WITH OPTICAL PATHWAY ([[US Patent Application 18447560. PACKAGED DEVICE WITH OPTICAL PATHWAY simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447560]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Hsien-Wei Chen | ||
+ | |||
+ | |||
+ | ===METHOD OF FABRICATING SEMICONDUCTOR STRUCTURE ([[US Patent Application 18362983. METHOD OF FABRICATING SEMICONDUCTOR STRUCTURE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18362983]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Feng-Wei KUO | ||
+ | |||
+ | |||
+ | ===FIBER TO CHIP COUPLER AND METHOD OF MAKING THE SAME ([[US Patent Application 18448032. FIBER TO CHIP COUPLER AND METHOD OF MAKING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18448032]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Chen-Hao HUANG | ||
+ | |||
+ | |||
+ | ===METHOD OF MAKING PHOTONIC DEVICE ([[US Patent Application 18448046. METHOD OF MAKING PHOTONIC DEVICE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18448046]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Chien-Ying WU | ||
+ | |||
+ | |||
+ | ===METHOD OF USING FIBER TO CHIP COUPLER AND METHOD OF MAKING ([[US Patent Application 18448095. METHOD OF USING FIBER TO CHIP COUPLER AND METHOD OF MAKING simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18448095]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Sui-Ying HSU | ||
+ | |||
+ | |||
+ | ===METHOD OF MAKING SEMICONDUCTOR DEVICE INCLUDING OPTICAL THROUGH VIA AND METHOD OF USING ([[US Patent Application 18358790. METHOD OF MAKING SEMICONDUCTOR DEVICE INCLUDING OPTICAL THROUGH VIA AND METHOD OF USING simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18358790]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Yu-Hao CHEN | ||
+ | |||
+ | |||
+ | ===STRUCTURES AND PROCESS FLOW FOR INTEGRATED PHOTONIC-ELECTRIC IC PACKAGE BY USING POLYMER WAVEGUIDE ([[US Patent Application 18232317. STRUCTURES AND PROCESS FLOW FOR INTEGRATED PHOTONIC-ELECTRIC IC PACKAGE BY USING POLYMER WAVEGUIDE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18232317]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Yu-Hao CHEN | ||
+ | |||
+ | |||
+ | ===Thermo-Electric Cooler for Dissipating Heat of Optical Engine ([[US Patent Application 17896249. Thermo-Electric Cooler for Dissipating Heat of Optical Engine simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17896249]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Hsing-Kuo Hsia | ||
+ | |||
+ | |||
+ | ===PELLICLE FOR AN EUV LITHOGRAPHY MASK AND A METHOD OF MANUFACTURING THEREOF ([[US Patent Application 18232674. PELLICLE FOR AN EUV LITHOGRAPHY MASK AND A METHOD OF MANUFACTURING THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18232674]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Yun-Yue LIN | ||
+ | |||
+ | |||
+ | ===EUV Lithography Mask With A Porous Reflective Multilayer Structure ([[US Patent Application 18366136. EUV Lithography Mask With A Porous Reflective Multilayer Structure simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18366136]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Chih-Tsung Shih | ||
+ | |||
+ | |||
+ | ===PHOTOMASK ASSEMBLY AND METHOD OF FORMING THE SAME ([[US Patent Application 18362046. PHOTOMASK ASSEMBLY AND METHOD OF FORMING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18362046]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Kuo-Hao LEE | ||
+ | |||
+ | |||
+ | ===SUB-RESOLUTION ASSIST FEATURES ([[US Patent Application 18447425. SUB-RESOLUTION ASSIST FEATURES simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447425]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Kenji Yamazoe | ||
+ | |||
+ | |||
+ | ===PHOTORESIST COMPOSITION AND METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE ([[US Patent Application 18232264. PHOTORESIST COMPOSITION AND METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18232264]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | An-Ren ZI | ||
+ | |||
+ | |||
+ | ===PHOTORESIST MATERIALS AND ASSOCIATED METHODS ([[US Patent Application 18447568. PHOTORESIST MATERIALS AND ASSOCIATED METHODS simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447568]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Ming-Hui WENG | ||
+ | |||
+ | |||
+ | ===PHOTORESIST COMPOSITION AND METHOD OF FORMING PHOTORESIST PATTERN ([[US Patent Application 18232225. PHOTORESIST COMPOSITION AND METHOD OF FORMING PHOTORESIST PATTERN simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18232225]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | An-Ren Zi | ||
+ | |||
+ | |||
+ | ===Polymer Layer in Semiconductor Device and Method of Manufacture ([[US Patent Application 18446562. Polymer Layer in Semiconductor Device and Method of Manufacture simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446562]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Sih-Hao Liao | ||
+ | |||
+ | |||
+ | ===PHOTORESIST COMPOSITION AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE ([[US Patent Application 18232220. PHOTORESIST COMPOSITION AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18232220]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Yen-Hao CHEN | ||
+ | |||
+ | |||
+ | ===UNDERLAYER COMPOSITION AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE ([[US Patent Application 18232774. UNDERLAYER COMPOSITION AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18232774]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Ming-Hui WENG | ||
+ | |||
+ | |||
+ | ===PHOTORESIST UNDER-LAYER AND METHOD OF FORMING PHOTORESIST PATTERN ([[US Patent Application 18232717. PHOTORESIST UNDER-LAYER AND METHOD OF FORMING PHOTORESIST PATTERN simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18232717]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | An-Ren ZI | ||
+ | |||
+ | |||
+ | ===SYSTEM AND METHOD FOR SUPPLYING AND DISPENSING BUBBLE-FREE PHOTOLITHOGRAPHY CHEMICAL SOLUTIONS ([[US Patent Application 18365529. SYSTEM AND METHOD FOR SUPPLYING AND DISPENSING BUBBLE-FREE PHOTOLITHOGRAPHY CHEMICAL SOLUTIONS simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18365529]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Wen-Zhan Zhou | ||
+ | |||
+ | |||
+ | ===APPARATUS, SYSTEM AND METHOD ([[US Patent Application 18447104. APPARATUS, SYSTEM AND METHOD simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447104]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Po-Han Wang | ||
+ | |||
+ | |||
+ | ===PHOTORESIST WITH POLAR-ACID-LABILE-GROUP ([[US Patent Application 18447441. PHOTORESIST WITH POLAR-ACID-LABILE-GROUP simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447441]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | An-Ren Zi | ||
+ | |||
+ | |||
+ | ===METHOD FOR REMOVING RESISTOR LAYER, AND METHOD OF MANUFACTURING SEMICONDUCTOR ([[US Patent Application 18358904. METHOD FOR REMOVING RESISTOR LAYER, AND METHOD OF MANUFACTURING SEMICONDUCTOR simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18358904]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Hung-Jui Kuo | ||
+ | |||
+ | |||
+ | ===SEMICONDUCTOR PROCESSING TOOL AND METHODS OF OPERATION ([[US Patent Application 18446870. SEMICONDUCTOR PROCESSING TOOL AND METHODS OF OPERATION simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446870]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Kai-Chieh CHANG | ||
+ | |||
+ | |||
+ | ===OPTIMIZED MASK STITCHING ([[US Patent Application 18231070. OPTIMIZED MASK STITCHING simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18231070]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Sagar TRIVEDI | ||
+ | |||
+ | |||
+ | ===OPTICAL PROXIMITY CORRECTION AND PHOTOMASKS ([[US Patent Application 18361879. OPTICAL PROXIMITY CORRECTION AND PHOTOMASKS simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18361879]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Dong-Yo Jheng | ||
+ | |||
+ | |||
+ | ===ENHANCING LITHOGRAPHY OPERATION FOR MANUFACTURING SEMICONDUCTOR DEVICES ([[US Patent Application 18232745. ENHANCING LITHOGRAPHY OPERATION FOR MANUFACTURING SEMICONDUCTOR DEVICES simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18232745]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Yih-Chen SU | ||
+ | |||
+ | |||
+ | ===MODULE VESSEL WITH SCRUBBER GUTTERS SIZED TO PREVENT OVERFLOW ([[US Patent Application 18447361. MODULE VESSEL WITH SCRUBBER GUTTERS SIZED TO PREVENT OVERFLOW simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447361]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Chun-Kai CHANG | ||
+ | |||
+ | |||
+ | ===SEMICONDUCTOR WAFER COOLING ([[US Patent Application 18362037. SEMICONDUCTOR WAFER COOLING simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18362037]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Yung-Yao LEE | ||
+ | |||
+ | |||
+ | ===MEMORY ADDRESS PROTECTION CIRCUIT AND METHOD OF OPERATING SAME ([[US Patent Application 18355222. MEMORY ADDRESS PROTECTION CIRCUIT AND METHOD OF OPERATING SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18355222]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Saman M. I. ADHAM | ||
+ | |||
+ | |||
+ | ===FAULT DIAGNOSTICS ([[US Patent Application 18303219. FAULT DIAGNOSTICS simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18303219]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Sandeep Kumar Goel | ||
+ | |||
+ | |||
+ | ===METHOD AND SYSTEM FOR SEMICONDUCTOR WAFER DEFECT REVIEW ([[US Patent Application 18447170. METHOD AND SYSTEM FOR SEMICONDUCTOR WAFER DEFECT REVIEW simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447170]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Chung-Pin CHOU | ||
+ | |||
+ | |||
+ | ===INTEGRATED CIRCUIT AND METHOD OF FORMING THE SAME ([[US Patent Application 17821559. INTEGRATED CIRCUIT AND METHOD OF FORMING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17821559]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Johnny Chiahao LI | ||
+ | |||
+ | |||
+ | ===METHOD FOR CHIP INTEGRATION ([[US Patent Application 17828648. METHOD FOR CHIP INTEGRATION simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17828648]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Yung Feng Chang | ||
+ | |||
+ | |||
+ | ===SEMICONDUCTOR DEVICE ([[US Patent Application 18361815. SEMICONDUCTOR DEVICE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18361815]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Yu-Jen CHEN | ||
+ | |||
+ | |||
+ | ===ANTI-FUSE ARRAY ([[US Patent Application 18446684. ANTI-FUSE ARRAY simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446684]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Meng-Sheng CHANG | ||
+ | |||
+ | |||
+ | ===INTEGRATED CIRCUIT AND METHOD OF MANUFACTURING THE SAME ([[US Patent Application 18446771. INTEGRATED CIRCUIT AND METHOD OF MANUFACTURING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446771]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Yu-Jung CHANG | ||
+ | |||
+ | |||
+ | ===METHOD OF GENERATING NETLIST INCLUDING PROXIMITY-EFFECT-INDUCER (PEI) PARAMETERS ([[US Patent Application 18447964. METHOD OF GENERATING NETLIST INCLUDING PROXIMITY-EFFECT-INDUCER (PEI) PARAMETERS simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447964]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Yen-Pin CHEN | ||
+ | |||
+ | |||
+ | ===SILICON PHOTONICS SYSTEM ([[US Patent Application 18155980. SILICON PHOTONICS SYSTEM simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18155980]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Feng-Wei KUO | ||
+ | |||
+ | |||
+ | ===INTEGRATED CIRCUIT AND METHOD OF FORMING THE SAME ([[US Patent Application 18354377. INTEGRATED CIRCUIT AND METHOD OF FORMING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18354377]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | John LIN | ||
+ | |||
+ | |||
+ | ===TRANSMISSION GATE STRUCTURE ([[US Patent Application 18362195. TRANSMISSION GATE STRUCTURE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18362195]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Shao-Lun CHIEN | ||
+ | |||
+ | |||
+ | ===DESIGN RULE CHECK VIOLATION PREDICTION SYSTEMS AND METHODS ([[US Patent Application 18446745. DESIGN RULE CHECK VIOLATION PREDICTION SYSTEMS AND METHODS simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446745]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Yi-Lin CHUANG | ||
+ | |||
+ | |||
+ | ===DESIGN RULE CHECK VIOLATION PREDICTION SYSTEMS AND METHODS ([[US Patent Application 18447455. DESIGN RULE CHECK VIOLATION PREDICTION SYSTEMS AND METHODS simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447455]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Yi-Lin CHUANG | ||
+ | |||
+ | |||
+ | ===SYSTEM AND METHOD FOR GENERATING LAYOUT DIAGRAM INCLUDING WIRING ARRANGEMENT ([[US Patent Application 18448143. SYSTEM AND METHOD FOR GENERATING LAYOUT DIAGRAM INCLUDING WIRING ARRANGEMENT simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18448143]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Fong-Yuan CHANG | ||
+ | |||
+ | |||
+ | ===METHOD AND APPARATUS FOR DEFECT-TOLERANT MEMORY-BASED ARTIFICIAL NEURAL NETWORK ([[US Patent Application 18231769. METHOD AND APPARATUS FOR DEFECT-TOLERANT MEMORY-BASED ARTIFICIAL NEURAL NETWORK simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18231769]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Win-San KHWA | ||
+ | |||
+ | |||
+ | ===NEUROMORPHIC COMPUTING DEVICE WITH THREE-DIMENSIONAL MEMORY ([[US Patent Application 17824306. NEUROMORPHIC COMPUTING DEVICE WITH THREE-DIMENSIONAL MEMORY simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17824306]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Chieh Lee | ||
+ | |||
+ | |||
+ | ===CIRCUITS AND METHODS FOR COMPENSATING A MISMATCH IN A SENSE AMPLIFIER ([[US Patent Application 18232768. CIRCUITS AND METHODS FOR COMPENSATING A MISMATCH IN A SENSE AMPLIFIER simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18232768]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Ku-Feng LIN | ||
+ | |||
+ | |||
+ | ===MEMORY DEVICE WITH SOURCE LINE CONTROL ([[US Patent Application 18232542. MEMORY DEVICE WITH SOURCE LINE CONTROL simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18232542]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Perng-Fei Yuh | ||
+ | |||
+ | |||
+ | ===Systems and Methods for Controlling Power Management Operations in a Memory Device ([[US Patent Application 18446818. Systems and Methods for Controlling Power Management Operations in a Memory Device simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446818]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Sanjeev Kumar Jain | ||
+ | |||
+ | |||
+ | ===ARRANGEMENTS OF MEMORY DEVICES AND METHODS OF OPERATING THE MEMORY DEVICES ([[US Patent Application 18446072. ARRANGEMENTS OF MEMORY DEVICES AND METHODS OF OPERATING THE MEMORY DEVICES simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446072]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Chien-Yuan Chen | ||
+ | |||
+ | |||
+ | ===FIRST FIRE OPERATION FOR OVONIC THRESHOLD SWITCH SELECTOR ([[US Patent Application 17826180. FIRST FIRE OPERATION FOR OVONIC THRESHOLD SWITCH SELECTOR simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17826180]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Elia Ambrosi | ||
+ | |||
+ | |||
+ | ===MEMORY DEVICE WITH REDUCED AREA ([[US Patent Application 17752662. MEMORY DEVICE WITH REDUCED AREA simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17752662]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Chun-Ying Lee | ||
+ | |||
+ | |||
+ | ===THREE-DIMENSIONAL ONE TIME PROGRAMMABLE MEMORY ([[US Patent Application 18232539. THREE-DIMENSIONAL ONE TIME PROGRAMMABLE MEMORY simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18232539]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Meng-Sheng Chang | ||
+ | |||
+ | |||
+ | ===NON-VOLATILE MEMORY CIRCUIT AND METHOD ([[US Patent Application 18448152. NON-VOLATILE MEMORY CIRCUIT AND METHOD simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18448152]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Gu-Huan LI | ||
+ | |||
+ | |||
+ | ===REPELLENT ELECTRODE FOR ELECTRON REPELLING ([[US Patent Application 18448026. REPELLENT ELECTRODE FOR ELECTRON REPELLING simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18448026]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Ching-Heng YEN | ||
+ | |||
+ | |||
+ | ===ATOM PROBE TOMOGRAPHY SPECIMEN PREPARATION ([[US Patent Application 18448014. ATOM PROBE TOMOGRAPHY SPECIMEN PREPARATION simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18448014]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Shih-Wei HUNG | ||
+ | |||
+ | |||
+ | ===FOCUS RING FOR A PLASMA-BASED SEMICONDUCTOR PROCESSING TOOL ([[US Patent Application 18447410. FOCUS RING FOR A PLASMA-BASED SEMICONDUCTOR PROCESSING TOOL simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447410]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Sheng-Chieh HUANG | ||
+ | |||
+ | |||
+ | ===DEVICE FOR ADJUSTING POSITION OF CHAMBER AND PLASMA PROCESS CHAMBER INCLUDING THE SAME FOR SEMICONDUCTOR MANUFACTURING ([[US Patent Application 18231165. DEVICE FOR ADJUSTING POSITION OF CHAMBER AND PLASMA PROCESS CHAMBER INCLUDING THE SAME FOR SEMICONDUCTOR MANUFACTURING simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18231165]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Ming Che CHEN | ||
+ | |||
+ | |||
+ | ===SYSTEM AND METHOD FOR PARTICLE CONTROL IN MRAM PROCESSING ([[US Patent Application 18231740. SYSTEM AND METHOD FOR PARTICLE CONTROL IN MRAM PROCESSING simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18231740]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Tsung-Han Kuo | ||
+ | |||
+ | |||
+ | ===SYSTEM AND METHOD FOR RESIDUAL GAS ANALYSIS ([[US Patent Application 18361767. SYSTEM AND METHOD FOR RESIDUAL GAS ANALYSIS simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18361767]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Yen-Liang CHEN | ||
+ | |||
+ | |||
+ | ===SYSTEM AND METHOD FOR RESIDUAL GAS ANALYSIS ([[US Patent Application 18361771. SYSTEM AND METHOD FOR RESIDUAL GAS ANALYSIS simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18361771]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Yen-Liang CHEN | ||
+ | |||
+ | |||
+ | ===SEMICONDUCTOR TOOL FOR COPPER DEPOSITION ([[US Patent Application 18447557. SEMICONDUCTOR TOOL FOR COPPER DEPOSITION simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447557]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Chia-Hung TSAI | ||
+ | |||
+ | |||
+ | ===METHOD FOR REDUCING CHARGING OF SEMICONDUCTOR WAFERS ([[US Patent Application 18225576. METHOD FOR REDUCING CHARGING OF SEMICONDUCTOR WAFERS simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18225576]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Wei-Lin CHANG | ||
+ | |||
+ | |||
+ | ===INTERCONNECT STRUCTURE FOR SEMICONDUCTOR DEVICES ([[US Patent Application 18359552. INTERCONNECT STRUCTURE FOR SEMICONDUCTOR DEVICES simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18359552]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Po-Chuan Wang | ||
+ | |||
+ | |||
+ | ===SEMICONDUCTOR DEVICE PRE-CLEANING ([[US Patent Application 17804447. SEMICONDUCTOR DEVICE PRE-CLEANING simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17804447]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Yi-Hsiang CHAO | ||
+ | |||
+ | |||
+ | ===APPARATUS FOR ELECTRO-CHEMICAL PLATING ([[US Patent Application 18231196. APPARATUS FOR ELECTRO-CHEMICAL PLATING simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18231196]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Kuo-Lung HOU | ||
+ | |||
+ | |||
+ | ===Forming Low-Stress Silicon Nitride Layer Through Hydrogen Treatment ([[US Patent Application 18358508. Forming Low-Stress Silicon Nitride Layer Through Hydrogen Treatment simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18358508]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Wei-Che Hsieh | ||
+ | |||
+ | |||
+ | ===SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURE ([[US Patent Application 18446953. SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446953]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Chun-Yen Peng | ||
+ | |||
+ | |||
+ | ===PRE-TREATMENT APPARATUS ([[US Patent Application 18188929. PRE-TREATMENT APPARATUS simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18188929]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Chun-Hsiang WANG | ||
+ | |||
+ | |||
+ | ===DEVICE AND METHOD FOR HIGH PRESSURE ANNEAL ([[US Patent Application 18365517. DEVICE AND METHOD FOR HIGH PRESSURE ANNEAL simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18365517]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Szu-Ying Chen | ||
+ | |||
+ | |||
+ | ===SYSTEM AND METHOD FOR MULTIPLE STEP DIRECTIONAL PATTERNING ([[US Patent Application 18447869. SYSTEM AND METHOD FOR MULTIPLE STEP DIRECTIONAL PATTERNING simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447869]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Chih-Kai YANG | ||
+ | |||
+ | |||
+ | ===METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES ([[US Patent Application 17829154. METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17829154]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Po-Han LIN | ||
+ | |||
+ | |||
+ | ===METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES ([[US Patent Application 18232758. METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18232758]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Chun-Wei LIAO | ||
+ | |||
+ | |||
+ | ===EUV PHOTOMASK AND RELATED METHODS ([[US Patent Application 18366397. EUV PHOTOMASK AND RELATED METHODS simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18366397]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Chi-Hung LIAO | ||
+ | |||
+ | |||
+ | ===Method of Forming a Semiconductor Device by Driving Hydrogen into a Dielectric Layer from Another Dielectric Layer ([[US Patent Application 18358609. Method of Forming a Semiconductor Device by Driving Hydrogen into a Dielectric Layer from Another Dielectric Layer simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18358609]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Hongfa Luan | ||
+ | |||
+ | |||
+ | ===SURFACE OXIDATION CONTROL OF METAL GATES USING CAPPING LAYER ([[US Patent Application 18230712. SURFACE OXIDATION CONTROL OF METAL GATES USING CAPPING LAYER simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18230712]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Pei-Yu Chou | ||
+ | |||
+ | |||
+ | ===AMBIENT CONTROLLED TWO-STEP THERMAL TREATMENT FOR SPIN-ON COATING LAYER PLANARIZATION ([[US Patent Application 18446416. AMBIENT CONTROLLED TWO-STEP THERMAL TREATMENT FOR SPIN-ON COATING LAYER PLANARIZATION simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446416]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Chen-Fong TSAI | ||
+ | |||
+ | |||
+ | ===Plasma-Assisted Etching Of Metal Oxides ([[US Patent Application 18447943. Plasma-Assisted Etching Of Metal Oxides simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447943]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Chansyun David YANG | ||
+ | |||
+ | |||
+ | ===METHODS FOR FORMING POLYCRYSTALLINE CHANNEL ON DIELECTRIC FILMS WITH CONTROLLED GRAIN BOUNDARIES ([[US Patent Application 18446415. METHODS FOR FORMING POLYCRYSTALLINE CHANNEL ON DIELECTRIC FILMS WITH CONTROLLED GRAIN BOUNDARIES simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446415]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Cheng-Hsien WU | ||
+ | |||
+ | |||
+ | ===METHOD FOR IMPROVED POLYSILICON ETCH DIMENSIONAL CONTROL ([[US Patent Application 18447810. METHOD FOR IMPROVED POLYSILICON ETCH DIMENSIONAL CONTROL simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447810]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Yun-Jui HE | ||
+ | |||
+ | |||
+ | ===NITRIDE-CONTAINING STI LINER FOR SIGE CHANNEL ([[US Patent Application 18446652. NITRIDE-CONTAINING STI LINER FOR SIGE CHANNEL simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446652]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Ya-Wen Chiu | ||
+ | |||
+ | |||
+ | ===SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURE ([[US Patent Application 18447389. SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447389]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Wei-Chih Chen | ||
+ | |||
+ | |||
+ | ===SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE ([[US Patent Application 18447409. SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447409]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Wei-Yu Chen | ||
+ | |||
+ | |||
+ | ===SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING ([[US Patent Application 18447443. SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447443]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Po-Chen Lai | ||
+ | |||
+ | |||
+ | ===STACKED SEMICONDUCTOR DEVICES AND METHODS OF FORMING SAME ([[US Patent Application 18447460. STACKED SEMICONDUCTOR DEVICES AND METHODS OF FORMING SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447460]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Hsien-Wei Chen | ||
+ | |||
+ | |||
+ | ===Semiconductor Package and Method of Forming Thereof ([[US Patent Application 18447428. Semiconductor Package and Method of Forming Thereof simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447428]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Jiun Yi Wu | ||
+ | |||
+ | |||
+ | ===CHEMICAL DISPENSING SYSTEM ([[US Patent Application 18447353. CHEMICAL DISPENSING SYSTEM simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447353]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Ming-Chieh HSU | ||
+ | |||
+ | |||
+ | ===UNDER BOAT SUPPORT WITH ELECTROSTATIC DISCHARGE STRUCTURE ([[US Patent Application 18162538. UNDER BOAT SUPPORT WITH ELECTROSTATIC DISCHARGE STRUCTURE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18162538]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Ying-Hao WANG | ||
+ | |||
+ | |||
+ | ===SYSTEMS AND METHODS FOR AIR FLOW OPTIMIZATION IN ENVIRONMENT FOR SEMICONDUCTOR DEVICE ([[US Patent Application 18358517. SYSTEMS AND METHODS FOR AIR FLOW OPTIMIZATION IN ENVIRONMENT FOR SEMICONDUCTOR DEVICE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18358517]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Yi-Fam Shiu | ||
+ | |||
+ | |||
+ | ===SEMICONDUCTOR PROCESSING METHOD AND APPARATUS ([[US Patent Application 18447519. SEMICONDUCTOR PROCESSING METHOD AND APPARATUS simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447519]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Shuang-Shiuan DENG | ||
+ | |||
+ | |||
+ | ===SYSTEM AND METHOD FOR RING FRAME CLEANING AND INSPECTION ([[US Patent Application 18231751. SYSTEM AND METHOD FOR RING FRAME CLEANING AND INSPECTION simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18231751]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Chien-Fa Lee | ||
+ | |||
+ | |||
+ | ===SEMICONDUCTOR STRUCTURE AND FORMING METHOD THEREOF ([[US Patent Application 18446549. SEMICONDUCTOR STRUCTURE AND FORMING METHOD THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446549]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Soon-Kang HUANG | ||
+ | |||
+ | |||
+ | ===ETCH METHOD FOR INTERCONNECT STRUCTURE ([[US Patent Application 18447134. ETCH METHOD FOR INTERCONNECT STRUCTURE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447134]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Chun-Cheng Chou | ||
+ | |||
+ | |||
+ | ===LOCAL INTERCONNECT ([[US Patent Application 18447549. LOCAL INTERCONNECT simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447549]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Cheng-Hsien Wu | ||
+ | |||
+ | |||
+ | ===SEMICONDUCTOR DEVICE STRUCTURE HAVING AIR GAP AND METHODS OF FORMING THE SAME ([[US Patent Application 18230338. SEMICONDUCTOR DEVICE STRUCTURE HAVING AIR GAP AND METHODS OF FORMING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18230338]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Ting-Ya LO | ||
+ | |||
+ | |||
+ | ===FINFET STRUCTURE WITH CONTROLLED AIR GAPS ([[US Patent Application 18360617. FINFET STRUCTURE WITH CONTROLLED AIR GAPS simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18360617]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Wen-Che Tsai | ||
+ | |||
+ | |||
+ | ===Semiconductor Device with Air Gaps and Method of Fabrication Thereof ([[US Patent Application 18446183. Semiconductor Device with Air Gaps and Method of Fabrication Thereof simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446183]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Chia-Hao Chang | ||
+ | |||
+ | |||
+ | ===Integrated Circuit Package and Method ([[US Patent Application 18446521. Integrated Circuit Package and Method simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446521]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Ting-Chen Tseng | ||
+ | |||
+ | |||
+ | ===Semiconductor Package Including Step Seal Ring and Methods Forming Same ([[US Patent Application 17819341. Semiconductor Package Including Step Seal Ring and Methods Forming Same simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17819341]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Sheng-Han Tsai | ||
+ | |||
+ | |||
+ | ===Methods of Performing Chemical-Mechanical Polishing Process in Semiconductor Devices ([[US Patent Application 18359486. Methods of Performing Chemical-Mechanical Polishing Process in Semiconductor Devices simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18359486]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Shih-Kang Fu | ||
+ | |||
+ | |||
+ | ===IMPROVED CONTACT RESISTANCE BETWEEN VIA AND CONDUCTIVE LINE ([[US Patent Application 18447084. IMPROVED CONTACT RESISTANCE BETWEEN VIA AND CONDUCTIVE LINE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447084]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Chun-Yuan Chen | ||
+ | |||
+ | |||
+ | ===Contact Structure For Semiconductor Device ([[US Patent Application 18232718. Contact Structure For Semiconductor Device simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18232718]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Hsu-Kai CHANG | ||
+ | |||
+ | |||
+ | ===SOURCE/DRAIN CONTACT FORMATION METHODS AND DEVICES ([[US Patent Application 18361770. SOURCE/DRAIN CONTACT FORMATION METHODS AND DEVICES simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18361770]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Cheng-Wei Chang | ||
+ | |||
+ | |||
+ | ===METHODS OF FORMING SEMICONDUCTOR DEVICE STRUCTURES ([[US Patent Application 17825307. METHODS OF FORMING SEMICONDUCTOR DEVICE STRUCTURES simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17825307]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Yu-Chen KO | ||
+ | |||
+ | |||
+ | ===METHOD FOR FORMING A CONTACT PLUG BY BOTTOM-UP METAL GROWTH ([[US Patent Application 17825678. METHOD FOR FORMING A CONTACT PLUG BY BOTTOM-UP METAL GROWTH simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17825678]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Chung-Liang CHENG | ||
+ | |||
+ | |||
+ | ===GATE CONTACT STRUCTURE ([[US Patent Application 18446326. GATE CONTACT STRUCTURE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446326]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Cheng-Chi Chuang | ||
+ | |||
+ | |||
+ | ===METHOD OF FORMING CONTACT METAL ([[US Patent Application 18360587. METHOD OF FORMING CONTACT METAL simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18360587]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Chun-Hsien Huang | ||
+ | |||
+ | |||
+ | ===SEMICONDUCTOR PACKAGE AND METHOD COMPRISING FORMATION OF REDISTRIBUTION STRUCTURE AND INTERCONNECTING DIE ([[US Patent Application 18446748. SEMICONDUCTOR PACKAGE AND METHOD COMPRISING FORMATION OF REDISTRIBUTION STRUCTURE AND INTERCONNECTING DIE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446748]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Jiun Yi Wu | ||
+ | |||
+ | |||
+ | ===METAL GATE PROCESS AND RELATED STRUCTURE ([[US Patent Application 17804146. METAL GATE PROCESS AND RELATED STRUCTURE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17804146]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Chih-Lun LU | ||
+ | |||
+ | |||
+ | ===SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE ([[US Patent Application 18446728. SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446728]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Chan Syun David Yang | ||
+ | |||
+ | |||
+ | ===METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE HAVING A DUMMY SECTION ([[US Patent Application 18360814. METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE HAVING A DUMMY SECTION simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18360814]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Osamu KOIKE | ||
+ | |||
+ | |||
+ | ===FinFETs With Epitaxy Regions Having Mixed Wavy and Non-Wavy Portions ([[US Patent Application 18361354. FinFETs With Epitaxy Regions Having Mixed Wavy and Non-Wavy Portions simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18361354]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Shahaji B. More | ||
+ | |||
+ | |||
+ | ===Semiconductor Device With Isolation Structures ([[US Patent Application 18232171. Semiconductor Device With Isolation Structures simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18232171]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Pei-Wei Lee | ||
+ | |||
+ | |||
+ | ===Semiconductor Device and Method of Manufacture ([[US Patent Application 18363945. Semiconductor Device and Method of Manufacture simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18363945]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Chia-Ching Lee | ||
+ | |||
+ | |||
+ | ===Local Gate Height Tuning by CMP and Dummy Gate Design ([[US Patent Application 18365405. Local Gate Height Tuning by CMP and Dummy Gate Design simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18365405]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Ming-Chang Wen | ||
+ | |||
+ | |||
+ | ===METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE ([[US Patent Application 18361501. METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18361501]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Chung-Ting KO | ||
+ | |||
+ | |||
+ | ===MULTI-LAYERED INSULATING FILM STACK ([[US Patent Application 18363439. MULTI-LAYERED INSULATING FILM STACK simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18363439]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Chieh-Ping Wang | ||
+ | |||
+ | |||
+ | ===SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF ([[US Patent Application 18447125. SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447125]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Shu-Uei Jang | ||
+ | |||
+ | |||
+ | ===Self-Aligned Structure For Semiconductor Devices ([[US Patent Application 18447922. Self-Aligned Structure For Semiconductor Devices simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447922]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Kuo-Cheng CHIANG | ||
+ | |||
+ | |||
+ | ===SEMICONDUCTOR DEVICE STRUCTURE WITH SOURCE/DRAIN STRUCTURE AND METHOD FOR FORMING THE SAME ([[US Patent Application 17824249. SEMICONDUCTOR DEVICE STRUCTURE WITH SOURCE/DRAIN STRUCTURE AND METHOD FOR FORMING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17824249]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Ta-Chun LIN | ||
+ | |||
+ | |||
+ | ===Dual Channel Gate All Around Transistor Device and Fabrication Methods Thereof ([[US Patent Application 18366562. Dual Channel Gate All Around Transistor Device and Fabrication Methods Thereof simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18366562]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Wei-Sheng Yun | ||
+ | |||
+ | |||
+ | ===REPLACEMENT GATE PROCESS FOR SEMICONDUCTOR DEVICES ([[US Patent Application 18359747. REPLACEMENT GATE PROCESS FOR SEMICONDUCTOR DEVICES simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18359747]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Yu-Jen Shen | ||
+ | |||
+ | |||
+ | ===HIGH-K DIELECTRIC MATERIALS WITH DIPOLE LAYER ([[US Patent Application 18447239. HIGH-K DIELECTRIC MATERIALS WITH DIPOLE LAYER simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447239]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Huiching Chang | ||
+ | |||
+ | |||
+ | ===METHOD FOR FORMING SEMICONDUCTOR STRUCTURE ([[US Patent Application 17824263. METHOD FOR FORMING SEMICONDUCTOR STRUCTURE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17824263]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Chih-Hsin Yang | ||
+ | |||
+ | |||
+ | ===MANUFACTURING PROCESS WITH ATOMIC LEVEL INSPECTION ([[US Patent Application 18359206. MANUFACTURING PROCESS WITH ATOMIC LEVEL INSPECTION simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18359206]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | I-Che Lee | ||
+ | |||
+ | |||
+ | ===DEPOSITION SYSTEM AND METHOD ([[US Patent Application 18361729. DEPOSITION SYSTEM AND METHOD simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18361729]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Wen-Hao CHENG | ||
+ | |||
+ | |||
+ | ===SYSTEMS AND METHODS OF TESTING MEMORY DEVICES ([[US Patent Application 18232518. SYSTEMS AND METHODS OF TESTING MEMORY DEVICES simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18232518]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Meng-Han Lin | ||
+ | |||
+ | |||
+ | ===SEMICONDUCTOR PACKAGE INCLUDING TEST LINE STRUCTURE ([[US Patent Application 18232520. SEMICONDUCTOR PACKAGE INCLUDING TEST LINE STRUCTURE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18232520]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Tsung-Yang Hsieh | ||
+ | |||
+ | |||
+ | ===SEMICONDUCTOR DEVICE AND METHOD ([[US Patent Application 18446591. SEMICONDUCTOR DEVICE AND METHOD simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446591]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Yin-Jie Pan | ||
+ | |||
+ | |||
+ | ===Package and Method for Forming the Same ([[US Patent Application 17828691. Package and Method for Forming the Same simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17828691]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Yu-Sheng Lin | ||
+ | |||
+ | |||
+ | ===SEMICONDUCTOR PACKAGE AND METHOD OF FORMING SAME ([[US Patent Application 18447416. SEMICONDUCTOR PACKAGE AND METHOD OF FORMING SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447416]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Ting-Chen Tseng | ||
+ | |||
+ | |||
+ | ===MANUFACTURING METHOD OF SEMICONDUCTOR PACKAGE ([[US Patent Application 18363742. MANUFACTURING METHOD OF SEMICONDUCTOR PACKAGE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18363742]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Meng-Liang Lin | ||
+ | |||
+ | |||
+ | ===STACKED SEMICONDUCTOR DEVICE INCLUDING A COOLING STRUCTURE ([[US Patent Application 18446076. STACKED SEMICONDUCTOR DEVICE INCLUDING A COOLING STRUCTURE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446076]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Jen-Yuan CHANG | ||
+ | |||
+ | |||
+ | ===SEMICONDUCTOR DEVICE HAVING A THERMAL CONTACT AND METHOD OF MAKING ([[US Patent Application 18447927. SEMICONDUCTOR DEVICE HAVING A THERMAL CONTACT AND METHOD OF MAKING simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447927]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Jian WU | ||
+ | |||
+ | |||
+ | ===SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF ([[US Patent Application 17827992. SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17827992]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Wei-Ming Wang | ||
+ | |||
+ | |||
+ | ===INVERTED TRAPEZOIDAL HEAT DISSIPATING SOLDER STRUCTURE AND METHOD OF MAKING THE SAME ([[US Patent Application 17829243. INVERTED TRAPEZOIDAL HEAT DISSIPATING SOLDER STRUCTURE AND METHOD OF MAKING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17829243]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Chang-Jung HSUEH | ||
+ | |||
+ | |||
+ | ===VIA CONNECTION STRUCTURE HAVING MULTIPLE VIA TO VIA CONNECTIONS ([[US Patent Application 17825336. VIA CONNECTION STRUCTURE HAVING MULTIPLE VIA TO VIA CONNECTIONS simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17825336]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Ting-Yu Yeh | ||
+ | |||
+ | |||
+ | ===Through-Circuit Vias In Interconnect Structures ([[US Patent Application 18232200. Through-Circuit Vias In Interconnect Structures simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18232200]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Jian-Hong LIN | ||
+ | |||
+ | |||
+ | ===SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF ([[US Patent Application 18361917. SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18361917]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Jen-Chun Liao | ||
+ | |||
+ | |||
+ | ===PACKAGE STRUCTURE AND METHOD OF FORMING THE SAME ([[US Patent Application 18446146. PACKAGE STRUCTURE AND METHOD OF FORMING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446146]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Chen-Hua Yu | ||
+ | |||
+ | |||
+ | ===Semiconductor Device Having Backside Interconnect Structure on Through Substrate Via ([[US Patent Application 18447871. Semiconductor Device Having Backside Interconnect Structure on Through Substrate Via simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447871]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Yung-Chi Lin | ||
+ | |||
+ | |||
+ | ===SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF ([[US Patent Application 18359864. SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18359864]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Ting-Yu Yeh | ||
+ | |||
+ | |||
+ | ===Semiconductor Device and Method of Manufacture ([[US Patent Application 18446006. Semiconductor Device and Method of Manufacture simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446006]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Jiun Yi Wu | ||
+ | |||
+ | |||
+ | ===SEMICONDUCTOR PACKAGE DIELECTRIC SUSBTRATE INCLUDING A TRENCH ([[US Patent Application 18232523. SEMICONDUCTOR PACKAGE DIELECTRIC SUSBTRATE INCLUDING A TRENCH simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18232523]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Yueh-Ting Lin | ||
+ | |||
+ | |||
+ | ===SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF ([[US Patent Application 18363766. SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18363766]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Chien-Hung Chen | ||
+ | |||
+ | |||
+ | ===Semiconductor Devices Including Decoupling Capacitors ([[US Patent Application 18446648. Semiconductor Devices Including Decoupling Capacitors simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446648]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Yu-Xuan Huang | ||
+ | |||
+ | |||
+ | ===SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF ([[US Patent Application 18446873. SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446873]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Chung-Ting Lu | ||
+ | |||
+ | |||
+ | ===BACK-END-OF-LINE PASSIVE DEVICE STRUCTURE ([[US Patent Application 18447722. BACK-END-OF-LINE PASSIVE DEVICE STRUCTURE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447722]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Tsung-Chieh Hsiao | ||
+ | |||
+ | |||
+ | ===SEMICONDUCTOR DEVICES WITH REDUCED EFFECT OF CAPACITIVE COUPLING ([[US Patent Application 17825698. SEMICONDUCTOR DEVICES WITH REDUCED EFFECT OF CAPACITIVE COUPLING simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17825698]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Chih-Yu Lu | ||
+ | |||
+ | |||
+ | ===SOURCE/DRAIN ISOLATION STRUCTURE, LAYOUT, AND METHOD ([[US Patent Application 17752704. SOURCE/DRAIN ISOLATION STRUCTURE, LAYOUT, AND METHOD simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17752704]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Chi-Yu LU | ||
+ | |||
+ | |||
+ | ===Functional Component Within Interconnect Structure of Semiconductor Device and Method of Forming Same ([[US Patent Application 18366771. Functional Component Within Interconnect Structure of Semiconductor Device and Method of Forming Same simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18366771]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Hsien-Wei Chen | ||
+ | |||
+ | |||
+ | ===CONDUCTIVE RAIL STRUCTURE FOR SEMICONDUCTOR DEVICES ([[US Patent Application 18447664. CONDUCTIVE RAIL STRUCTURE FOR SEMICONDUCTOR DEVICES simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447664]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Yi-Bo LIAO | ||
+ | |||
+ | |||
+ | ===DIAGONAL VIA STRUCTURE ([[US Patent Application 18448125. DIAGONAL VIA STRUCTURE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18448125]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Shih-Wei PENG | ||
+ | |||
+ | |||
+ | ===DUAL-MODE WIRELESS CHARGING DEVICE ([[US Patent Application 18232312. DUAL-MODE WIRELESS CHARGING DEVICE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18232312]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Shih-Wei LIANG | ||
+ | |||
+ | |||
+ | ===SEMICONDUCTOR DEVICE INCLUDING BACK SIDE POWER SUPPLY CIRCUIT ([[US Patent Application 18232306. SEMICONDUCTOR DEVICE INCLUDING BACK SIDE POWER SUPPLY CIRCUIT simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18232306]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Gerben DOORNBOS | ||
+ | |||
+ | |||
+ | ===ADVANCED NODE INTERCONNECT ROUTING METHODOLOGY ([[US Patent Application 18446025. ADVANCED NODE INTERCONNECT ROUTING METHODOLOGY simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446025]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Shih-Wei Peng | ||
+ | |||
+ | |||
+ | ===Semiconductor Structures And Methods Of Forming The Same ([[US Patent Application 18446113. Semiconductor Structures And Methods Of Forming The Same simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446113]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Lin-Yu Huang | ||
+ | |||
+ | |||
+ | ===FIRST METAL STRUCTURE, LAYOUT, AND METHOD ([[US Patent Application 17752737. FIRST METAL STRUCTURE, LAYOUT, AND METHOD simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17752737]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Chi-Yu LU | ||
+ | |||
+ | |||
+ | ===Semiconductor Devices Including Backside Power Via and Methods of Forming the Same ([[US Patent Application 17819679. Semiconductor Devices Including Backside Power Via and Methods of Forming the Same simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17819679]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Po-Hsien Cheng | ||
+ | |||
+ | |||
+ | ===POWER RAIL AND SIGNAL LINE ARRANGEMENT IN INTEGRATED CIRCUITS HAVING STACKED TRANSISTORS ([[US Patent Application 18361666. POWER RAIL AND SIGNAL LINE ARRANGEMENT IN INTEGRATED CIRCUITS HAVING STACKED TRANSISTORS simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18361666]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Chih-Liang CHEN | ||
+ | |||
+ | |||
+ | ===METHOD OF MANUFACTURING INTEGRATED CIRCUIT ([[US Patent Application 18447572. METHOD OF MANUFACTURING INTEGRATED CIRCUIT simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447572]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Chih-Yu LAI | ||
+ | |||
+ | |||
+ | ===CELL STRUCTURE WITH INTERMEDIATE METAL LAYERS FOR POWER SUPPLIES ([[US Patent Application 18448005. CELL STRUCTURE WITH INTERMEDIATE METAL LAYERS FOR POWER SUPPLIES simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18448005]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Li-Chun Tien | ||
+ | |||
+ | |||
+ | ===METHOD OF MAKING SEMICONDUCTOR DEVICE INCLUDING BURIED CONDUCTIVE FINGERS ([[US Patent Application 18448028. METHOD OF MAKING SEMICONDUCTOR DEVICE INCLUDING BURIED CONDUCTIVE FINGERS simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18448028]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Chih-Liang CHEN | ||
+ | |||
+ | |||
+ | ===Liner-Free Conductive Structures With Anchor Points ([[US Patent Application 18232722. Liner-Free Conductive Structures With Anchor Points simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18232722]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Hsu-Kai Chang | ||
+ | |||
+ | |||
+ | ===GRAPHENE LAYER FOR REDUCED CONTACT RESISTANCE ([[US Patent Application 18359383. GRAPHENE LAYER FOR REDUCED CONTACT RESISTANCE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18359383]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Shin-Yi Yang | ||
+ | |||
+ | |||
+ | ===INTEGRATED CHIP WITH GRAPHENE BASED INTERCONNECT ([[US Patent Application 18360012. INTEGRATED CHIP WITH GRAPHENE BASED INTERCONNECT simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18360012]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Shin-Yi Yang | ||
+ | |||
+ | |||
+ | ===INTERCONNECT STRUCTURE INCLUDING CHARGED DIELECTRIC LAYERS ([[US Patent Application 17825345. INTERCONNECT STRUCTURE INCLUDING CHARGED DIELECTRIC LAYERS simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17825345]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Chien Hung Liu | ||
+ | |||
+ | |||
+ | ===SEMICONDUCTOR DEVICE INCLUDING INTERCONNECTS WITH LOWER CONTACT RESISTANCE ([[US Patent Application 17825741. SEMICONDUCTOR DEVICE INCLUDING INTERCONNECTS WITH LOWER CONTACT RESISTANCE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17825741]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Hsi-Wen TIEN | ||
+ | |||
+ | |||
+ | ===SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF ([[US Patent Application 18446753. SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446753]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Hung-Ming CHEN | ||
+ | |||
+ | |||
+ | ===DUAL-SIDED ROUTING IN 3D SIP STRUCTURE ([[US Patent Application 18447769. DUAL-SIDED ROUTING IN 3D SIP STRUCTURE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447769]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Po-Hao Tsai | ||
+ | |||
+ | |||
+ | ===SEMICONDUCTOR PACKAGE DEVICE AND SEMICONDUCTOR WIRING SUBSTRATE THEREOF ([[US Patent Application 17823063. SEMICONDUCTOR PACKAGE DEVICE AND SEMICONDUCTOR WIRING SUBSTRATE THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17823063]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Sheng-Fan YANG | ||
+ | |||
+ | |||
+ | ===SEMICONDUCTOR PACKAGE CROSSTALK REDUCTION ([[US Patent Application 17824353. SEMICONDUCTOR PACKAGE CROSSTALK REDUCTION simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17824353]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Shu-Chun Yang | ||
+ | |||
+ | |||
+ | ===Semiconductor Devices With Backside Power Distribution Network And Frontside Through Silicon Via ([[US Patent Application 18232713. Semiconductor Devices With Backside Power Distribution Network And Frontside Through Silicon Via simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18232713]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Kam-Tou SIO | ||
+ | |||
+ | |||
+ | ===SEMICONDUCTOR DEVICE AND METHOD OF MAKING THE SAME ([[US Patent Application 18230999. SEMICONDUCTOR DEVICE AND METHOD OF MAKING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18230999]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Cheng-Chieh HSIEH | ||
+ | |||
+ | |||
+ | ===SEMICONDCUTOR PACKAGES AND METHODS OF FORMING THEREOF ([[US Patent Application 17881128. SEMICONDCUTOR PACKAGES AND METHODS OF FORMING THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17881128]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Sung-Yueh Wu | ||
+ | |||
+ | |||
+ | ===Antenna Apparatus and Method ([[US Patent Application 18366282. Antenna Apparatus and Method simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18366282]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Feng-Wei Kuo | ||
+ | |||
+ | |||
+ | ===POLYIMIDE PROFILE CONTROL ([[US Patent Application 18446834. POLYIMIDE PROFILE CONTROL simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446834]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Chen-Chi HUANG | ||
+ | |||
+ | |||
+ | ===BONDING STRUCTURES OF INTEGRATED CIRCUIT DEVICES AND METHOD FORMING THE SAME ([[US Patent Application 18446028. BONDING STRUCTURES OF INTEGRATED CIRCUIT DEVICES AND METHOD FORMING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446028]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Chen-Yu Tsai | ||
+ | |||
+ | |||
+ | ===INTEGRATED CIRCUIT PACKAGE AND METHOD ([[US Patent Application 18365362. INTEGRATED CIRCUIT PACKAGE AND METHOD simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18365362]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Wen-Chih Chiou | ||
+ | |||
+ | |||
+ | ===SEMICONDUCTOR DIE PACKAGE AND METHOD OF MANUFACTURE ([[US Patent Application 18446732. SEMICONDUCTOR DIE PACKAGE AND METHOD OF MANUFACTURE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446732]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Kuan-Yu Huang | ||
+ | |||
+ | |||
+ | ===INTEGRATED CIRCUIT PACKAGE AND METHOD OF FORMING SAME ([[US Patent Application 17664689. INTEGRATED CIRCUIT PACKAGE AND METHOD OF FORMING SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17664689]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Yu-Sheng Lin | ||
+ | |||
+ | |||
+ | ===Storage Layers For Wafer Bonding ([[US Patent Application 18447968. Storage Layers For Wafer Bonding simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447968]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | De-Yang CHIOU | ||
+ | |||
+ | |||
+ | ===System and Method for Bonding Semiconductor Devices ([[US Patent Application 18359416. System and Method for Bonding Semiconductor Devices simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18359416]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Kai-Tai Chang | ||
+ | |||
+ | |||
+ | ===SEMICONDUCTOR STRUCTURE WITH INTEGRATED PASSIVE DEVICE HAVING OPPOSED SOLDER BUMPS ([[US Patent Application 17824330. SEMICONDUCTOR STRUCTURE WITH INTEGRATED PASSIVE DEVICE HAVING OPPOSED SOLDER BUMPS simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17824330]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Fong-yuan Chang | ||
+ | |||
+ | |||
+ | ===SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF ([[US Patent Application 18361953. SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18361953]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Chung-Liang CHENG | ||
+ | |||
+ | |||
+ | ===System Formed Through Package-In-Package Formation ([[US Patent Application 18362649. System Formed Through Package-In-Package Formation simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18362649]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Chen-Hua Yu | ||
+ | |||
+ | |||
+ | ===Semiconductor Devices and Methods of Manufacturing ([[US Patent Application 18446291. Semiconductor Devices and Methods of Manufacturing simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446291]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Chang-Yi Yang | ||
+ | |||
+ | |||
+ | ===Integrated Circuit Packages and Methods of Forming the Same ([[US Patent Application 17828310. Integrated Circuit Packages and Methods of Forming the Same simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17828310]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Pei-Haw Tsao | ||
+ | |||
+ | |||
+ | ===METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE HAVING STAGGERED GATE-STUB-SIZE PROFILE AND SYSTEM FOR SAME ([[US Patent Application 18447979. METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE HAVING STAGGERED GATE-STUB-SIZE PROFILE AND SYSTEM FOR SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447979]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Te-Hsin CHIU | ||
+ | |||
+ | |||
+ | ===Stacked Semiconductor Device and Method ([[US Patent Application 18359578. Stacked Semiconductor Device and Method simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18359578]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Min-Feng Kao | ||
+ | |||
+ | |||
+ | ===SEMICONDUCTOR DEVICE ([[US Patent Application 18362030. SEMICONDUCTOR DEVICE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18362030]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Chung-Te LIN | ||
+ | |||
+ | |||
+ | ===INTEGRATED CIRCUIT WITH BACKSIDE TRENCH FOR METAL GATE DEFINITION ([[US Patent Application 18447881. INTEGRATED CIRCUIT WITH BACKSIDE TRENCH FOR METAL GATE DEFINITION simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447881]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Kuo-Cheng CHIANG | ||
+ | |||
+ | |||
+ | ===Profile Control Of Gate Structures In Semiconductor Devices ([[US Patent Application 18232181. Profile Control Of Gate Structures In Semiconductor Devices simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18232181]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Kai-Chi WU | ||
+ | |||
+ | |||
+ | ===Semiconductor Device and Method ([[US Patent Application 18359492. Semiconductor Device and Method simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18359492]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Jen-Chih Hsueh | ||
+ | |||
+ | |||
+ | ===FIN END ISOLATION STRUCTURE FOR SEMICONDUCTOR DEVICES ([[US Patent Application 18360007. FIN END ISOLATION STRUCTURE FOR SEMICONDUCTOR DEVICES simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18360007]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | JHON JHY Liaw | ||
+ | |||
+ | |||
+ | ===Semiconductor Devices Having Gate Dielectric Layers of Varying Thicknesses and Methods of Forming the Same ([[US Patent Application 18360166. Semiconductor Devices Having Gate Dielectric Layers of Varying Thicknesses and Methods of Forming the Same simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18360166]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Ta-Chun Lin | ||
+ | |||
+ | |||
+ | ===Backside Power Rail And Methods Of Forming The Same ([[US Patent Application 18360895. Backside Power Rail And Methods Of Forming The Same simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18360895]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Huan-Chieh Su | ||
+ | |||
+ | |||
+ | ===SEMICONDUCTOR DEVICE STRUCTURE WITH AIR GAP AND METHOD FOR FORMING THE SAME ([[US Patent Application 17826604. SEMICONDUCTOR DEVICE STRUCTURE WITH AIR GAP AND METHOD FOR FORMING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17826604]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Yi-Ruei JHAN | ||
+ | |||
+ | |||
+ | ===SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAME ([[US Patent Application 18229682. SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18229682]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Jui-Chien HUANG | ||
+ | |||
+ | |||
+ | ===Multi-Gate Device Integration with Separated Fin-Like Field Effect Transistor Cells and Gate-All-Around Transistor Cells ([[US Patent Application 18360118. Multi-Gate Device Integration with Separated Fin-Like Field Effect Transistor Cells and Gate-All-Around Transistor Cells simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18360118]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Jhon Jhy Liaw | ||
+ | |||
+ | |||
+ | ===SEMICONDUCTOR DEVICES WITH DIELECTRIC FINS AND METHOD FOR FORMING THE SAME ([[US Patent Application 18361704. SEMICONDUCTOR DEVICES WITH DIELECTRIC FINS AND METHOD FOR FORMING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18361704]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Kuan-Ting Pan | ||
+ | |||
+ | |||
+ | ===SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF ([[US Patent Application 18362862. SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18362862]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Yu-Lien HUANG | ||
+ | |||
+ | |||
+ | ===SEMICONDUCTOR DEVICE AND METHOD ([[US Patent Application 18365391. SEMICONDUCTOR DEVICE AND METHOD simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18365391]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Shahaji B. More | ||
+ | |||
+ | |||
+ | ===SEMICONDUCTOR STRUCTURE WITH SELF-ALIGNED BACKSIDE POWER RAIL ([[US Patent Application 18366004. SEMICONDUCTOR STRUCTURE WITH SELF-ALIGNED BACKSIDE POWER RAIL simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18366004]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Kuo-Cheng Chiang | ||
+ | |||
+ | |||
+ | ===INTEGRATED CIRCUIT AND METHOD OF FORMING THE SAME ([[US Patent Application 17828981. INTEGRATED CIRCUIT AND METHOD OF FORMING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17828981]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Chin-Wei HSU | ||
+ | |||
+ | |||
+ | ===INTEGRATED CIRCUIT WITH ACTIVE REGION JOGS ([[US Patent Application 18362868. INTEGRATED CIRCUIT WITH ACTIVE REGION JOGS simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18362868]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Tian-Yu XIE | ||
+ | |||
+ | |||
+ | ===LOW-COST SEMICONDUCTOR-ON-INSULATOR (SOI) STRUCTURE ([[US Patent Application 18366831. LOW-COST SEMICONDUCTOR-ON-INSULATOR (SOI) STRUCTURE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18366831]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Harry-Hak-Lay Chuang | ||
+ | |||
+ | |||
+ | ===METAL GRID STRUCTURE TO IMPROVE IMAGE SENSOR PERFORMANCE ([[US Patent Application 18360214. METAL GRID STRUCTURE TO IMPROVE IMAGE SENSOR PERFORMANCE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18360214]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Ming Chyi Liu | ||
+ | |||
+ | |||
+ | ===IMAGE SENSOR WITH A HIGH ABSORPTION LAYER ([[US Patent Application 18364662. IMAGE SENSOR WITH A HIGH ABSORPTION LAYER simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18364662]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Chien-Chang Huang | ||
+ | |||
+ | |||
+ | ===PIXEL SENSOR INCLUDING A TRANSFER FINFET ([[US Patent Application 18447340. PIXEL SENSOR INCLUDING A TRANSFER FINFET simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447340]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Feng-Chien HSIEH | ||
+ | |||
+ | |||
+ | ===EMBEDDED LIGHT SHIELD STRUCTURE FOR CMOS IMAGE SENSOR ([[US Patent Application 18364667. EMBEDDED LIGHT SHIELD STRUCTURE FOR CMOS IMAGE SENSOR simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18364667]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Shih-Hsun Hsu | ||
+ | |||
+ | |||
+ | ===IMAGE SENSOR WITH PASSIVATION LAYER FOR DARK CURRENT REDUCTION ([[US Patent Application 18446572. IMAGE SENSOR WITH PASSIVATION LAYER FOR DARK CURRENT REDUCTION simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446572]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Hsiang-Lin Chen | ||
+ | |||
+ | |||
+ | ===METHOD FOR FORMING LIGHT PIPE STRUCTURE WITH HIGH QUANTUM EFFICIENCY ([[US Patent Application 18360966. METHOD FOR FORMING LIGHT PIPE STRUCTURE WITH HIGH QUANTUM EFFICIENCY simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18360966]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Tsun-Kai Tsao | ||
+ | |||
+ | |||
+ | ===OPTICAL BIOSENSOR DEVICE WITH OPTICAL SIGNAL ENHANCEMENT STRUCTURE ([[US Patent Application 17824183. OPTICAL BIOSENSOR DEVICE WITH OPTICAL SIGNAL ENHANCEMENT STRUCTURE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17824183]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Yi-Hsien Chang | ||
+ | |||
+ | |||
+ | ===IMAGE SENSOR DEVICE ([[US Patent Application 18362866. IMAGE SENSOR DEVICE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18362866]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Yun-Wei CHENG | ||
+ | |||
+ | |||
+ | ===BACK-SIDE DEEP TRENCH ISOLATION STRUCTURE FOR IMAGE SENSOR ([[US Patent Application 18364682. BACK-SIDE DEEP TRENCH ISOLATION STRUCTURE FOR IMAGE SENSOR simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18364682]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Cheng-Ta Wu | ||
+ | |||
+ | |||
+ | ===DEEP TRENCH ISOLATION STRUCTURE IN A PIXEL SENSOR ([[US Patent Application 18364734. DEEP TRENCH ISOLATION STRUCTURE IN A PIXEL SENSOR simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18364734]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Feng-Chien HSIEH | ||
+ | |||
+ | |||
+ | ===Anchor Structures And Methods For Uniform Wafer Planarization And Bonding ([[US Patent Application 18232751. Anchor Structures And Methods For Uniform Wafer Planarization And Bonding simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18232751]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Chia-Yu Wei | ||
+ | |||
+ | |||
+ | ===SYSTEMS AND METHODS FOR SHIELDED INDUCTIVE DEVICES ([[US Patent Application 18232332. SYSTEMS AND METHODS FOR SHIELDED INDUCTIVE DEVICES simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18232332]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Feng Wei KUO | ||
+ | |||
+ | |||
+ | ===INDUCTIVE DEVICE ([[US Patent Application 18447482. INDUCTIVE DEVICE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447482]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Wei-Yu CHOU | ||
+ | |||
+ | |||
+ | ===Resistor Structure ([[US Patent Application 18358557. Resistor Structure simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18358557]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Chih-Fan Huang | ||
+ | |||
+ | |||
+ | ===A MULTI-LAYERED RESISTOR WITH A TIGHT TEMPERATURE COEFFICIENT OF RESISTANCE TOLERANCE ([[US Patent Application 18366156. A MULTI-LAYERED RESISTOR WITH A TIGHT TEMPERATURE COEFFICIENT OF RESISTANCE TOLERANCE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18366156]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Szu-Hsien Lo | ||
+ | |||
+ | |||
+ | ===HIGH DENSITY METAL INSULATOR METAL CAPACITOR ([[US Patent Application 18231754. HIGH DENSITY METAL INSULATOR METAL CAPACITOR simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18231754]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Wei Kai SHIH | ||
+ | |||
+ | |||
+ | ===SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF ([[US Patent Application 17824436. SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17824436]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Tsung-Chieh HSIAO | ||
+ | |||
+ | |||
+ | ===SUPER JUNCTION STRUCTURE ([[US Patent Application 18448013. SUPER JUNCTION STRUCTURE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18448013]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Shuai ZHANG | ||
+ | |||
+ | |||
+ | ===NOVEL SOI DEVICE STRUCTURE FOR ROBUST ISOLATION ([[US Patent Application 18232545. NOVEL SOI DEVICE STRUCTURE FOR ROBUST ISOLATION simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18232545]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Lin-Chen Lu | ||
+ | |||
+ | |||
+ | ===SOURCE/DRAIN SPACER WITH AIR GAP IN SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME ([[US Patent Application 18366210. SOURCE/DRAIN SPACER WITH AIR GAP IN SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18366210]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Ko-Cheng Liu | ||
+ | |||
+ | |||
+ | ===SEMICONDUCTOR DEVICE WITH CORNER ISOLATION PROTECTION AND METHODS OF FORMING THE SAME ([[US Patent Application 18446665. SEMICONDUCTOR DEVICE WITH CORNER ISOLATION PROTECTION AND METHODS OF FORMING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446665]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Bwo-Ning Chen | ||
+ | |||
+ | |||
+ | ===SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME ([[US Patent Application 17824329. SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17824329]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Lin-Yu HUANG | ||
+ | |||
+ | |||
+ | ===SEMICONDUCTOR DEVICE AND METHOD ([[US Patent Application 18359695. SEMICONDUCTOR DEVICE AND METHOD simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18359695]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Hsin-Yi Lee | ||
+ | |||
+ | |||
+ | ===GALLIUM NITRIDE DRAIN STRUCTURES AND METHODS OF FORMING THE SAME ([[US Patent Application 17804751. GALLIUM NITRIDE DRAIN STRUCTURES AND METHODS OF FORMING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17804751]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Chi-Ming CHEN | ||
+ | |||
+ | |||
+ | ===EPITAXIAL SOURCE/DRAIN STRUCTURE WITH HIGH DOPANT CONCENTRATION ([[US Patent Application 17824915. EPITAXIAL SOURCE/DRAIN STRUCTURE WITH HIGH DOPANT CONCENTRATION simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17824915]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Chih Sheng Huang | ||
+ | |||
+ | |||
+ | ===INTEGRATION OF LOW AND HIGH VOLTAGE DEVICES ON SUBSTRATE ([[US Patent Application 18363077. INTEGRATION OF LOW AND HIGH VOLTAGE DEVICES ON SUBSTRATE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18363077]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Hsin Fu Lin | ||
+ | |||
+ | |||
+ | ===SEMICONDUCTOR DEVICES AND METHODS FOR FABRICATION THEREOF ([[US Patent Application 17752211. SEMICONDUCTOR DEVICES AND METHODS FOR FABRICATION THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17752211]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Jui-Lin CHANG | ||
+ | |||
+ | |||
+ | ===Semiconductor Gate-All-Around Device ([[US Patent Application 18360080. Semiconductor Gate-All-Around Device simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18360080]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Jhon Jhy Liaw | ||
+ | |||
+ | |||
+ | ===SILICON-GERMANIUM FINS AND METHODS OF PROCESSING THE SAME IN FIELD-EFFECT TRANSISTORS ([[US Patent Application 18447149. SILICON-GERMANIUM FINS AND METHODS OF PROCESSING THE SAME IN FIELD-EFFECT TRANSISTORS simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447149]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Yu-Shan Lu | ||
+ | |||
+ | |||
+ | ===PROCESS AND STRUCTURE FOR SOURCE/DRAIN CONTACTS ([[US Patent Application 18361262. PROCESS AND STRUCTURE FOR SOURCE/DRAIN CONTACTS simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18361262]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Meng-Huan Jao | ||
+ | |||
+ | |||
+ | ===SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE ([[US Patent Application 18447053. SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447053]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Chun-Hsien Huang | ||
+ | |||
+ | |||
+ | ===SEMICONDUCTOR DEVICE AND METHOD ([[US Patent Application 18447212. SEMICONDUCTOR DEVICE AND METHOD simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447212]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Po-Chuan Wang | ||
+ | |||
+ | |||
+ | ===SEMICONDUCTOR STRUCTURE WITH WRAPAROUND BACKSIDE AMORPHOUS LAYER ([[US Patent Application 18446864. SEMICONDUCTOR STRUCTURE WITH WRAPAROUND BACKSIDE AMORPHOUS LAYER simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446864]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Shih-Chuan Chiu | ||
+ | |||
+ | |||
+ | ===SEMICONDUCTOR DEVICES WITH BACKSIDE VIA AND METHODS THEREOF ([[US Patent Application 18360085. SEMICONDUCTOR DEVICES WITH BACKSIDE VIA AND METHODS THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18360085]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Po-Yu Huang | ||
+ | |||
+ | |||
+ | ===SEMICONDUCTOR DEVICE INTERCONNECTS AND METHODS OF FORMATION ([[US Patent Application 18447344. SEMICONDUCTOR DEVICE INTERCONNECTS AND METHODS OF FORMATION simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447344]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Te-Chih HSIUNG | ||
+ | |||
+ | |||
+ | ===CONTACT PLUG STRUCTURE OF SEMICONDUCTOR DEVICE AND METHOD OF FORMING SAME ([[US Patent Application 18366469. CONTACT PLUG STRUCTURE OF SEMICONDUCTOR DEVICE AND METHOD OF FORMING SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18366469]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Pei-Yu Chou | ||
+ | |||
+ | |||
+ | ===NOVEL STRUCTURE FOR METAL GATE ELECTRODE AND METHOD OF FABRICATION ([[US Patent Application 18446567. NOVEL STRUCTURE FOR METAL GATE ELECTRODE AND METHOD OF FABRICATION simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446567]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Ru-Shang Hsiao | ||
+ | |||
+ | |||
+ | ===Interconnect Features With Sharp Corners and Method Forming Same ([[US Patent Application 18366352. Interconnect Features With Sharp Corners and Method Forming Same simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18366352]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Tze-Liang Lee | ||
+ | |||
+ | |||
+ | ===METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES AND SEMICONDUCTOR DEVICES ([[US Patent Application 17752461. METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES AND SEMICONDUCTOR DEVICES simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17752461]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Yung-Hsiang CHAN | ||
+ | |||
+ | |||
+ | ===NANO TRANSISTORS WITH SOURCE/DRAIN HAVING SIDE CONTACTS TO 2-D MATERIAL ([[US Patent Application 18365995. NANO TRANSISTORS WITH SOURCE/DRAIN HAVING SIDE CONTACTS TO 2-D MATERIAL simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18365995]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Chao-Ching Cheng | ||
+ | |||
+ | |||
+ | ===MULTIGATE DEVICE WITH AIR GAP SPACER AND BACKSIDE RAIL CONTACT AND METHOD OF FABRICATING THEREOF ([[US Patent Application 18446151. MULTIGATE DEVICE WITH AIR GAP SPACER AND BACKSIDE RAIL CONTACT AND METHOD OF FABRICATING THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446151]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Guan-Lin CHEN | ||
+ | |||
+ | |||
+ | ===SEMICONDUCTOR DEVICE INCLUDING GRAPHENE BARRIER AND METHOD OF FORMING THE SAME ([[US Patent Application 17825411. SEMICONDUCTOR DEVICE INCLUDING GRAPHENE BARRIER AND METHOD OF FORMING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17825411]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Shin-Yi YANG | ||
+ | |||
+ | |||
+ | ===SOURCE/DRAIN SILICIDE FOR MULTIGATE DEVICE PERFORMANCE AND METHOD OF FABRICATING THEREOF ([[US Patent Application 18447183. SOURCE/DRAIN SILICIDE FOR MULTIGATE DEVICE PERFORMANCE AND METHOD OF FABRICATING THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447183]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Chih-Ching Wang | ||
+ | |||
+ | |||
+ | ===SCHOTTKY DIODE AND METHOD OF FABRICATION THEREOF ([[US Patent Application 17804125. SCHOTTKY DIODE AND METHOD OF FABRICATION THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17804125]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Wen-Shun LO | ||
+ | |||
+ | |||
+ | ===Spacer Structures for Nano-Sheet-Based Devices ([[US Patent Application 18446733. Spacer Structures for Nano-Sheet-Based Devices simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446733]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Shih-Cheng Chen | ||
+ | |||
+ | |||
+ | ===PARTIAL METAL GRAIN SIZE CONTROL TO IMPROVE CMP LOADING EFFECT ([[US Patent Application 18447685. PARTIAL METAL GRAIN SIZE CONTROL TO IMPROVE CMP LOADING EFFECT simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447685]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Anhao CHENG | ||
+ | |||
+ | |||
+ | ===Gate Spacers In Semiconductor Devices ([[US Patent Application 18232191. Gate Spacers In Semiconductor Devices simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18232191]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Wei-Liang LU | ||
+ | |||
+ | |||
+ | ===METHODS OF FORMING GATE STRUCTURES WITH UNIFORM GATE LENGTH ([[US Patent Application 18446958. METHODS OF FORMING GATE STRUCTURES WITH UNIFORM GATE LENGTH simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446958]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Shahaji B. More | ||
+ | |||
+ | |||
+ | ===Semiconductor Device with Air-Spacer ([[US Patent Application 18446190. Semiconductor Device with Air-Spacer simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446190]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Wei-Yang Lee | ||
+ | |||
+ | |||
+ | ===3D CAPACITOR AND METHOD OF MANUFACTURING SAME ([[US Patent Application 18366596. 3D CAPACITOR AND METHOD OF MANUFACTURING SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18366596]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Chi-Wen LIU | ||
+ | |||
+ | |||
+ | ===GATE PROFILE MODULATION FOR SEMICONDUCTOR DEVICE ([[US Patent Application 17824690. GATE PROFILE MODULATION FOR SEMICONDUCTOR DEVICE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17824690]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Tien-Shun CHANG | ||
+ | |||
+ | |||
+ | ===SELF-ALIGNED INNER SPACER ON GATE-ALL-AROUND STRUCTURE AND METHODS OF FORMING THE SAME ([[US Patent Application 18359597. SELF-ALIGNED INNER SPACER ON GATE-ALL-AROUND STRUCTURE AND METHODS OF FORMING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18359597]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Tsungyu Hung | ||
+ | |||
+ | |||
+ | ===TRANSISTOR ISOLATION STRUCTURES ([[US Patent Application 18446674. TRANSISTOR ISOLATION STRUCTURES simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446674]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Mrunal Abhijith KHADERBAD | ||
+ | |||
+ | |||
+ | ===SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THEREOF ([[US Patent Application 18446632. SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446632]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Chih-Hsuan Lin | ||
+ | |||
+ | |||
+ | ===CIRCUIT DEVICES WITH GATE SEALS ([[US Patent Application 18447467. CIRCUIT DEVICES WITH GATE SEALS simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447467]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Sheng-Chou Lai | ||
+ | |||
+ | |||
+ | ===TRANSISTOR SPACER STRUCTURES ([[US Patent Application 18447680. TRANSISTOR SPACER STRUCTURES simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447680]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Chansyun David YANG | ||
+ | |||
+ | |||
+ | ===Optimized Proximity Profile for Strained Source/Drain Feature and Method of Fabricating Thereof ([[US Patent Application 18446998. Optimized Proximity Profile for Strained Source/Drain Feature and Method of Fabricating Thereof simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446998]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Chun-An Lin | ||
+ | |||
+ | |||
+ | ===SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF ([[US Patent Application 17826174. SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17826174]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Wang-Chun Huang | ||
+ | |||
+ | |||
+ | ===Channel Structures For Semiconductor Devices ([[US Patent Application 18232159. Channel Structures For Semiconductor Devices simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18232159]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Ding-Kang SHIH | ||
+ | |||
+ | |||
+ | ===Controlling Fin-Thinning Through Feedback ([[US Patent Application 18361540. Controlling Fin-Thinning Through Feedback simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18361540]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Tsu-Hui Su | ||
+ | |||
+ | |||
+ | ===Liner for A Bi-Layer Gate Helmet and the Fabrication Thereof ([[US Patent Application 18365315. Liner for A Bi-Layer Gate Helmet and the Fabrication Thereof simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18365315]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Huan-Chieh Su | ||
+ | |||
+ | |||
+ | ===Nanowire Stack GAA Device with Inner Spacer and Methods for Producing the Same ([[US Patent Application 18366297. Nanowire Stack GAA Device with Inner Spacer and Methods for Producing the Same simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18366297]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Tzu-Chung Wang | ||
+ | |||
+ | |||
+ | ===STRUCTURE FOR REDUCING SOURCE/DRAIN CONTACT RESISTANCE AT WAFER BACKSIDE ([[US Patent Application 18366370. STRUCTURE FOR REDUCING SOURCE/DRAIN CONTACT RESISTANCE AT WAFER BACKSIDE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18366370]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Huan-Chieh Su | ||
+ | |||
+ | |||
+ | ===SEMICONDUCTOR DEVICE AND METHOD ([[US Patent Application 18446905. SEMICONDUCTOR DEVICE AND METHOD simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446905]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Shahaji B. More | ||
+ | |||
+ | |||
+ | ===Isolation Structures Of Semiconductor Devices ([[US Patent Application 18447953. Isolation Structures Of Semiconductor Devices simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447953]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Jia-Chuan You | ||
+ | |||
+ | |||
+ | ===EPITAXIAL STRUCTURES FOR FIN-LIKE FIELD EFFECT TRANSISTORS ([[US Patent Application 18359542. EPITAXIAL STRUCTURES FOR FIN-LIKE FIELD EFFECT TRANSISTORS simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18359542]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Chia-Ta Yu | ||
+ | |||
+ | |||
+ | ===METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE ([[US Patent Application 18232289. METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18232289]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Chia-Chi YU | ||
+ | |||
+ | |||
+ | ===SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF ([[US Patent Application 18232544. SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18232544]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Shih-Yao LIN | ||
+ | |||
+ | |||
+ | ===SYSTEM AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES ([[US Patent Application 18446738. SYSTEM AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446738]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Chia-Ao Chang | ||
+ | |||
+ | |||
+ | ===SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURE ([[US Patent Application 18447489. SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447489]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Wei-Chih KAO | ||
+ | |||
+ | |||
+ | ===Method of Gap Filling for Semiconductor Device ([[US Patent Application 18447618. Method of Gap Filling for Semiconductor Device simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447618]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Te-Yang Lai | ||
+ | |||
+ | |||
+ | ===GATED METAL-INSULATOR-SEMICONDUCTOR (MIS) TUNNEL DIODE HAVING NEGATIVE TRANSCONDUCTANCE ([[US Patent Application 18361758. GATED METAL-INSULATOR-SEMICONDUCTOR (MIS) TUNNEL DIODE HAVING NEGATIVE TRANSCONDUCTANCE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18361758]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Jenn-Gwo Hwu | ||
+ | |||
+ | |||
+ | ===INTEGRATION OF P-CHANNEL AND N-CHANNEL E-FET III-V DEVICES WITH OPTIMIZATION OF DEVICE PERFORMANCE ([[US Patent Application 18364679. INTEGRATION OF P-CHANNEL AND N-CHANNEL E-FET III-V DEVICES WITH OPTIMIZATION OF DEVICE PERFORMANCE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18364679]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Man-Ho Kwan | ||
+ | |||
+ | |||
+ | ===FERROELECTRIC FIELD EFFECT TRANSISTOR AND METHODS OF FORMING THE SAME ([[US Patent Application 17827755. FERROELECTRIC FIELD EFFECT TRANSISTOR AND METHODS OF FORMING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17827755]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Gerben Doornbos | ||
+ | |||
+ | |||
+ | ===SEMICONDUCTOR DEVICE AND METHOD ([[US Patent Application 18447153. SEMICONDUCTOR DEVICE AND METHOD simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447153]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Bo-Feng Young | ||
+ | |||
+ | |||
+ | ===DEVICES WITH STRAINED ISOLATION FEATURES ([[US Patent Application 18446960. DEVICES WITH STRAINED ISOLATION FEATURES simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446960]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Xusheng Wu | ||
+ | |||
+ | |||
+ | ===SOURCE/DRAIN FEATURES WITH IMPROVED STRAIN PROPERTIES ([[US Patent Application 18447483. SOURCE/DRAIN FEATURES WITH IMPROVED STRAIN PROPERTIES simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447483]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Chih-Ching Wang | ||
+ | |||
+ | |||
+ | ===SPACER STRUCTURES FOR SEMICONDUCTOR DEVICES ([[US Patent Application 18227712. SPACER STRUCTURES FOR SEMICONDUCTOR DEVICES simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18227712]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Cheng-Yi PENG | ||
+ | |||
+ | |||
+ | ===METHOD OF FABRICATING A SOURCE/DRAIN RECESS IN A SEMICONDUCTOR DEVICE ([[US Patent Application 18446539. METHOD OF FABRICATING A SOURCE/DRAIN RECESS IN A SEMICONDUCTOR DEVICE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446539]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Eric PENG | ||
+ | |||
+ | |||
+ | ===SEMICONDUCTOR DEVICE WITH SELF-ALIGNED WAVY CONTACT PROFILE AND METHOD OF FORMING THE SAME ([[US Patent Application 18447855. SEMICONDUCTOR DEVICE WITH SELF-ALIGNED WAVY CONTACT PROFILE AND METHOD OF FORMING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447855]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Chia-Ta Yu | ||
+ | |||
+ | |||
+ | ===HIGH-VOLTAGE SEMICONDUCTOR DEVICES AND METHODS OF FORMATION ([[US Patent Application 17804438. HIGH-VOLTAGE SEMICONDUCTOR DEVICES AND METHODS OF FORMATION simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17804438]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Jhu-Min SONG | ||
+ | |||
+ | |||
+ | ===Ferroelectric Semiconductor Device and Method ([[US Patent Application 18447453. Ferroelectric Semiconductor Device and Method simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447453]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Chia-Cheng Ho | ||
+ | |||
+ | |||
+ | ===ISOLATION STRUCTURES AND METHODS OF FORMING THE SAME IN FIELD-EFFECT TRANSISTORS ([[US Patent Application 18446664. ISOLATION STRUCTURES AND METHODS OF FORMING THE SAME IN FIELD-EFFECT TRANSISTORS simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446664]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Shi Ning Ju | ||
+ | |||
+ | |||
+ | ===SEMICONDUCTOR DEVICE HAVING ISOLATION STRUCTURE TO REDUCE CURRENT LEAKAGE ([[US Patent Application 17824669. SEMICONDUCTOR DEVICE HAVING ISOLATION STRUCTURE TO REDUCE CURRENT LEAKAGE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17824669]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Hung-Yu YEN | ||
+ | |||
+ | |||
+ | ===SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME ([[US Patent Application 17825516. SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17825516]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Shuen-Shin LIANG | ||
+ | |||
+ | |||
+ | ===Semiconductor Device With Fish Bone Structure And Methods Of Forming The Same ([[US Patent Application 18359280. Semiconductor Device With Fish Bone Structure And Methods Of Forming The Same simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18359280]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Chih-Chuan Yang | ||
+ | |||
+ | |||
+ | ===SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME ([[US Patent Application 18359690. SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18359690]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Marcus Johannes Henricus VAN DAL | ||
+ | |||
+ | |||
+ | ===SEMICONDUCTOR DEVICE AND METHOD ([[US Patent Application 18446918. SEMICONDUCTOR DEVICE AND METHOD simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446918]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Chunchieh Wang | ||
+ | |||
+ | |||
+ | ===METHOD OF MAKING DECOUPLING CAPACITOR ([[US Patent Application 18447194. METHOD OF MAKING DECOUPLING CAPACITOR simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447194]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Szu-Lin LIU | ||
+ | |||
+ | |||
+ | ===SEMICONDUCTOR DEVICE INCLUDING DEEP TRENCH CAPACITORS AND VIA CONTACTS ([[US Patent Application 17827251. SEMICONDUCTOR DEVICE INCLUDING DEEP TRENCH CAPACITORS AND VIA CONTACTS simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17827251]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Po-Chia Lai | ||
+ | |||
+ | |||
+ | ===DECOUPLING FINFET CAPACITORS ([[US Patent Application 18358464. DECOUPLING FINFET CAPACITORS simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18358464]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Chung-Hui Chen | ||
+ | |||
+ | |||
+ | ===VOLTAGE AMPLIFIER BASED ON CASCADED CHARGE PUMP BOOSTING ([[US Patent Application 18446031. VOLTAGE AMPLIFIER BASED ON CASCADED CHARGE PUMP BOOSTING simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446031]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Chin-Ho Chang | ||
+ | |||
+ | |||
+ | ===CLOCK GATING CIRCUIT AND METHOD OF OPERATING THE SAME ([[US Patent Application 18362916. CLOCK GATING CIRCUIT AND METHOD OF OPERATING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18362916]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Seid Hadi RASOULI | ||
+ | |||
+ | |||
+ | ===DATA RETENTION CIRCUIT AND METHOD ([[US Patent Application 18363192. DATA RETENTION CIRCUIT AND METHOD simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18363192]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Kai-Chi HUANG | ||
+ | |||
+ | |||
+ | ===Flip Flop Circuit ([[US Patent Application 18366981. Flip Flop Circuit simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18366981]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Po-Chia Lai | ||
+ | |||
+ | |||
+ | ===SYSTEM AND SEMICONDUCTOR DEVICE THEREIN ([[US Patent Application 17828834. SYSTEM AND SEMICONDUCTOR DEVICE THEREIN simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17828834]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Tsung-Che LU | ||
+ | |||
+ | |||
+ | ===POST-DRIVER WITH LOW VOLTAGE OPERATION AND ELECTROSTATIC DISCHARGE PROTECTION ([[US Patent Application 17828581. POST-DRIVER WITH LOW VOLTAGE OPERATION AND ELECTROSTATIC DISCHARGE PROTECTION simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17828581]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Chin-Hua Wen | ||
+ | |||
+ | |||
+ | ===Semiconductor Device Including a Level Shifter and Method of Mitigating a Delay Between Input and Output Signals ([[US Patent Application 18446849. Semiconductor Device Including a Level Shifter and Method of Mitigating a Delay Between Input and Output Signals simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446849]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Jerrin Pathrose Vareed | ||
+ | |||
+ | |||
+ | ===Semiconductor Device Including a Level Shifter and Method of Mitigating a Delay Between Input and Output Signals ([[US Patent Application 18447372. Semiconductor Device Including a Level Shifter and Method of Mitigating a Delay Between Input and Output Signals simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447372]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Jerrin Pathrose Vareed | ||
+ | |||
+ | |||
+ | ===Systems and Methods for Phase Locked Loop Realignment With Skew Cancellation ([[US Patent Application 18446881. Systems and Methods for Phase Locked Loop Realignment With Skew Cancellation simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446881]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Tsung-Hsien Tsai | ||
+ | |||
+ | |||
+ | ===Programmable Regulator Voltage Controlled Ring Oscillator ([[US Patent Application 18366742. Programmable Regulator Voltage Controlled Ring Oscillator simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18366742]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Tsung-Hsien Tsai | ||
+ | |||
+ | |||
+ | ===Circuits and Methods for a Noise Shaping Analog To Digital Converter ([[US Patent Application 18361949. Circuits and Methods for a Noise Shaping Analog To Digital Converter simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18361949]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Martin Kinyua | ||
+ | |||
+ | |||
+ | ===RADIO FREQUENCY SWITCH ([[US Patent Application 18231772. RADIO FREQUENCY SWITCH simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18231772]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Jun-De JIN | ||
+ | |||
+ | |||
+ | ===METHOD OF USING INTEGRATED TRANSMITTER AND RECEIVER FRONT END MODULE ([[US Patent Application 18361816. METHOD OF USING INTEGRATED TRANSMITTER AND RECEIVER FRONT END MODULE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18361816]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | En-Hsiang YEH | ||
+ | |||
+ | |||
+ | ===METHOD AND APPARATUS FOR LOGIC CELL-BASED PUF GENERATORS ([[US Patent Application 18232336. METHOD AND APPARATUS FOR LOGIC CELL-BASED PUF GENERATORS simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18232336]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Shih-Lien Linus LU | ||
+ | |||
+ | |||
+ | ===EUV LIGHT SOURCE AND APPARATUS FOR LITHOGRAPHY ([[US Patent Application 18231017. EUV LIGHT SOURCE AND APPARATUS FOR LITHOGRAPHY simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18231017]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Shang-Chieh CHIEN | ||
+ | |||
+ | |||
+ | ===SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME ([[US Patent Application 17826225. SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17826225]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Chun-Hung CHEN | ||
+ | |||
+ | |||
+ | ===IC INCLUDING STANDARD CELLS AND SRAM CELLS ([[US Patent Application 18361185. IC INCLUDING STANDARD CELLS AND SRAM CELLS simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18361185]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Jhon-Jhy LIAW | ||
+ | |||
+ | |||
+ | ===SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF ([[US Patent Application 18446094. SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446094]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Shih-Yao Lin | ||
+ | |||
+ | |||
+ | ===STATIC RANDOM ACCESS MEMORY WITH PRE-CHARGE CIRCUIT ([[US Patent Application 18446546. STATIC RANDOM ACCESS MEMORY WITH PRE-CHARGE CIRCUIT simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446546]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Po-Sheng WANG | ||
+ | |||
+ | |||
+ | ===MULTI-LAYER HIGH-K GATE DIELECTRIC STRUCTURE ([[US Patent Application 18446593. MULTI-LAYER HIGH-K GATE DIELECTRIC STRUCTURE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446593]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Chih-Yu Hsu | ||
+ | |||
+ | |||
+ | ===SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF ([[US Patent Application 17828123. SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17828123]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Jhon-Jhy LIAW | ||
+ | |||
+ | |||
+ | ===MEMORY DEVICES AND METHODS FOR OPERATING THE SAME ([[US Patent Application 17752580. MEMORY DEVICES AND METHODS FOR OPERATING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17752580]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Hsiang-Wei Liu | ||
+ | |||
+ | |||
+ | ===MEMORY DEVICE WITH IMPROVED ANTI-FUSE READ CURRENT ([[US Patent Application 18447638. MEMORY DEVICE WITH IMPROVED ANTI-FUSE READ CURRENT simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447638]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Meng-Sheng CHANG | ||
+ | |||
+ | |||
+ | ===SEMICONDUCTOR MEMORY DEVICES AND METHODS OF MANUFACTURING THEREOF ([[US Patent Application 18361249. SEMICONDUCTOR MEMORY DEVICES AND METHODS OF MANUFACTURING THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18361249]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Meng-Han Lin | ||
+ | |||
+ | |||
+ | ===Polysilicon Removal In Word Line Contact Region Of Memory Devices ([[US Patent Application 18447965. Polysilicon Removal In Word Line Contact Region Of Memory Devices simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447965]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Yen-Jou WU | ||
+ | |||
+ | |||
+ | ===MEMORY DEVICE AND MANUFACTURING METHOD THEREOF ([[US Patent Application 18446582. MEMORY DEVICE AND MANUFACTURING METHOD THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446582]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Feng-Ching Chu | ||
+ | |||
+ | |||
+ | ===FERROELECTRIC-BASED MEMORY DEVICE AND METHOD OF FORMING THE SAME ([[US Patent Application 18181229. FERROELECTRIC-BASED MEMORY DEVICE AND METHOD OF FORMING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18181229]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Yi-Hsuan Chen | ||
+ | |||
+ | |||
+ | ===MEMORY DEVICES AND METHODS OF MANUFACTURING THEREOF ([[US Patent Application 18361548. MEMORY DEVICES AND METHODS OF MANUFACTURING THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18361548]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Meng-Han Lin | ||
+ | |||
+ | |||
+ | ===THREE-DIMENSIONAL MEMORY DEVICE AND METHOD ([[US Patent Application 18366740. THREE-DIMENSIONAL MEMORY DEVICE AND METHOD simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18366740]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Chia-Yu Ling | ||
+ | |||
+ | |||
+ | ===THREE-DIMENSIONAL MEMORY DEVICES AND METHODS OF MANUFACTURING THEREOF ([[US Patent Application 18446894. THREE-DIMENSIONAL MEMORY DEVICES AND METHODS OF MANUFACTURING THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446894]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Meng-Han Lin | ||
+ | |||
+ | |||
+ | ===SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME ([[US Patent Application 18358966. SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18358966]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Gerben Doornbos | ||
+ | |||
+ | |||
+ | ===Memory Array and Methods of Forming Same ([[US Patent Application 18365068. Memory Array and Methods of Forming Same simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18365068]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Yu-Ming Lin | ||
+ | |||
+ | |||
+ | ===SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE ([[US Patent Application 18447495. SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447495]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Meng-Han Lin | ||
+ | |||
+ | |||
+ | ===MEMORY CELL ISOLATION ([[US Patent Application 17826100. MEMORY CELL ISOLATION simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17826100]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Tzu-Yu Chen | ||
+ | |||
+ | |||
+ | ===EMBEDDED BACKSIDE MEMORY ON A FIELD EFFECT TRANSISTOR ([[US Patent Application 18446557. EMBEDDED BACKSIDE MEMORY ON A FIELD EFFECT TRANSISTOR simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446557]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Kuan-Liang Liu | ||
+ | |||
+ | |||
+ | ===Memory Device and Methods of Forming Same ([[US Patent Application 18446586. Memory Device and Methods of Forming Same simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446586]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Chenchen Jacob Wang | ||
+ | |||
+ | |||
+ | ===METHOD OF FORMING SEMICONDUCTOR MEMORY DEVICE ([[US Patent Application 17825440. METHOD OF FORMING SEMICONDUCTOR MEMORY DEVICE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17825440]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Wei-Chih WEN | ||
+ | |||
+ | |||
+ | ===METHOD OF MANUFACTURING SEMICONDUCTOR STRUCTURE ([[US Patent Application 18448100. METHOD OF MANUFACTURING SEMICONDUCTOR STRUCTURE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18448100]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Yu-Hao CHEN | ||
+ | |||
+ | |||
+ | ===SELF-ALIGNED ENCAPSULATION HARD MASK TO SEPARATE PHYSICALLY UNDER-ETCHED MTJ CELLS TO REDUCE CONDUCTIVE RE-DEPOSITION ([[US Patent Application 18232027. SELF-ALIGNED ENCAPSULATION HARD MASK TO SEPARATE PHYSICALLY UNDER-ETCHED MTJ CELLS TO REDUCE CONDUCTIVE RE-DEPOSITION simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18232027]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Yi Yang | ||
+ | |||
+ | |||
+ | ===Metal/Dielectric/Metal Hybrid Hard Mask To Define Ultra-Large Height Top Electrode For Sub 60nm MRAM Devices ([[US Patent Application 18361677. Metal/Dielectric/Metal Hybrid Hard Mask To Define Ultra-Large Height Top Electrode For Sub 60nm MRAM Devices simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18361677]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Yi Yang | ||
+ | |||
+ | |||
+ | ===SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FORMING THE SAME ([[US Patent Application 18361832. SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FORMING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18361832]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Hsiang-Ku Shen | ||
+ | |||
+ | |||
+ | ===MRAM Fabrication and Device ([[US Patent Application 18447383. MRAM Fabrication and Device simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447383]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Jung-Tang Wu | ||
+ | |||
+ | |||
+ | ===MEMORY DEVICE AND METHOD OF FABRICATING THE SAME ([[US Patent Application 17827998. MEMORY DEVICE AND METHOD OF FABRICATING THE SAME simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17827998]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Yen-Lin Huang | ||
+ | |||
+ | |||
+ | ===MAGNETIC MEMORY DEVICE AND MANUFACTURING METHOD THEREOF ([[US Patent Application 17900892. MAGNETIC MEMORY DEVICE AND MANUFACTURING METHOD THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|17900892]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Ming-Yuan Song | ||
+ | |||
+ | |||
+ | ===MEMORY DEVICE AND FABRICATION METHOD THEREOF ([[US Patent Application 18446703. MEMORY DEVICE AND FABRICATION METHOD THEREOF simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446703]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Jun-Yao CHEN | ||
+ | |||
+ | |||
+ | ===SIDEWALL SPACER STRUCTURE FOR MEMORY CELL ([[US Patent Application 18364697. SIDEWALL SPACER STRUCTURE FOR MEMORY CELL simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18364697]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Yao-Wen Chang | ||
+ | |||
+ | |||
+ | ===MAGNETIC TUNNEL JUNCTION STRUCTURES WITH PROTECTION OUTER LAYERS ([[US Patent Application 18446398. MAGNETIC TUNNEL JUNCTION STRUCTURES WITH PROTECTION OUTER LAYERS simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446398]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Sheng-Chang CHEN | ||
+ | |||
+ | |||
+ | ===STRUCTURE AND METHOD FOR MRAM DEVICES ([[US Patent Application 18446563. STRUCTURE AND METHOD FOR MRAM DEVICES simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18446563]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Tsung-Chieh Hsiao | ||
+ | |||
+ | |||
+ | ===MAGNETIC TUNNELING JUNCTION WITH SYNTHETIC FREE LAYER FOR SOT-MRAM ([[US Patent Application 18447912. MAGNETIC TUNNELING JUNCTION WITH SYNTHETIC FREE LAYER FOR SOT-MRAM simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447912]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Chien-Min Lee | ||
+ | |||
+ | |||
+ | ===SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURE ([[US Patent Application 18447232. SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURE simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18447232]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Tung-Ying Lee | ||
+ | |||
+ | |||
+ | ===MEMORY DEVICE STRUCTURE WITH DATA STORAGE ELEMENT ([[US Patent Application 18358685. MEMORY DEVICE STRUCTURE WITH DATA STORAGE ELEMENT simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18358685]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Hai-Dang TRINH | ||
+ | |||
+ | |||
+ | ===METHODS OF FORMING MEMORY DEVICES ([[US Patent Application 18363751. METHODS OF FORMING MEMORY DEVICES simplified abstract (Taiwan Semiconductor Manufacturing Company, Ltd.)|18363751]])=== | ||
+ | |||
+ | |||
+ | '''Main Inventor''' | ||
+ | |||
+ | Hung-Li Chiang |
Latest revision as of 06:35, 7 December 2023
Summary of the patent applications from Taiwan Semiconductor Manufacturing Company, Ltd. on November 30th, 2023
Taiwan Semiconductor Manufacturing Company, Ltd. (TSMC) has recently filed several patents related to the formation and structure of memory devices and semiconductor devices. These patents aim to improve the performance, functionality, and efficiency of these devices.
Summary: - TSMC has filed patents for methods of forming memory devices, semiconductor devices, and magnetic memory devices. - The methods involve the formation of specific layers, plugs, and structures to enhance the functionality and performance of the devices. - The patents also describe the use of magnetic materials, spin-orbit torque induction structures, and magnetic tunnel junction stacks to improve the operation of the devices. - TSMC's patents also include methods for etching magnetic tunneling junction structures and creating ultra-large height top electrodes for MRAM devices. - The organization has also filed patents for semiconductor structures with optical components and thermal control mechanisms. - Notable applications of these patents include data storage, magnetic sensors, and magnetoresistive random-access memory (MRAM) devices.
Bullet points:
- TSMC has filed patents for memory devices, semiconductor devices, and magnetic memory devices.
- The patents describe methods for forming specific layers, plugs, and structures to enhance device performance.
- Magnetic materials, spin-orbit torque induction structures, and magnetic tunnel junction stacks are used in the devices.
- Patents also cover methods for etching magnetic tunneling junction structures and creating large height top electrodes for MRAM devices.
- Semiconductor structures with optical components and thermal control mechanisms are also described.
- Applications include data storage, magnetic sensors, and MRAM devices.
Contents
- 1 Patent applications for Taiwan Semiconductor Manufacturing Company, Ltd. on November 30th, 2023
- 1.1 PARTICLE REMOVER AND METHOD (18448963)
- 1.2 TRANSDUCER DEVICE AND METHOD OF MANUFACTURE (17752558)
- 1.3 DEVICE FOR FORMING CONDUCTIVE POWDER (18447161)
- 1.4 POLISHING METROLOGY (17898163)
- 1.5 CHEMICAL MECHANICAL POLISHING APPARATUS AND METHOD (18446842)
- 1.6 SYSTEM AND METHOD FOR REMOVING DEBRIS DURING CHEMICAL MECHANICAL PLANARIZATION (18447211)
- 1.7 MICROELECTROMECHANICAL SYSTEMS DEVICE HAVING A MECHANICALLY ROBUST ANTI-STICTION/OUTGASSING STRUCTURE (18364702)
- 1.8 MEMS MICROPHONE AND MEMS ACCELEROMETER ON A SINGLE SUBSTRATE (18446741)
- 1.9 WIRE-BOND DAMPER FOR SHOCK ABSORPTION (18446740)
- 1.10 DIELECTRIC PROTECTION LAYER CONFIGURED TO INCREASE PERFORMANCE OF MEMS DEVICE (17825225)
- 1.11 SHUTTER DISC FOR A SEMICONDUCTOR PROCESSING TOOL (18447543)
- 1.12 STRUCTURES AND METHODS FOR PROCESSING A SEMICONDUCTOR SUBSTRATE (18446392)
- 1.13 DEPOSITION SYSTEM AND METHOD (18447911)
- 1.14 Apparatus and Method for Use with a Substrate Chamber (18447493)
- 1.15 APPARATUS FOR STORING AND TRANSPORTING SEMICONDUCTOR ELEMENTS, AND METHOD OF MAKING THE SAME (18231763)
- 1.16 WAFER DRYING SYSTEM (18446858)
- 1.17 TEMPERATURE SENSOR CIRCUITS AND CONTROL CIRCUITS AND METHOD FOR TEMPERATURE SENSOR CIRCUITS (18150772)
- 1.18 TEMPERATURE SENSING BASED ON METAL RAILS WITH DIFFERENT THERMAL-RESISTANCE COEFFICIENTS (18170401)
- 1.19 CAPACITOR-BASED TEMPERATURE-SENSING DEVICE (18232329)
- 1.20 ON-LINE ANALYSIS SYSTEM AND METHOD FOR SPECIALTY GASSES (17752730)
- 1.21 IN-SITU APPARATUS FOR DETECTING ABNORMALITY IN PROCESS TUBE (18361777)
- 1.22 INTEGRATED BIOLOGICAL SENSING PLATFORM (18232318)
- 1.23 On-Chip Heater (18232719)
- 1.24 STRUCTURE AND PROCESS FOR PHOTONIC PACKAGES (18366758)
- 1.25 PACKAGED DEVICE WITH OPTICAL PATHWAY (18447560)
- 1.26 METHOD OF FABRICATING SEMICONDUCTOR STRUCTURE (18362983)
- 1.27 FIBER TO CHIP COUPLER AND METHOD OF MAKING THE SAME (18448032)
- 1.28 METHOD OF MAKING PHOTONIC DEVICE (18448046)
- 1.29 METHOD OF USING FIBER TO CHIP COUPLER AND METHOD OF MAKING (18448095)
- 1.30 METHOD OF MAKING SEMICONDUCTOR DEVICE INCLUDING OPTICAL THROUGH VIA AND METHOD OF USING (18358790)
- 1.31 STRUCTURES AND PROCESS FLOW FOR INTEGRATED PHOTONIC-ELECTRIC IC PACKAGE BY USING POLYMER WAVEGUIDE (18232317)
- 1.32 Thermo-Electric Cooler for Dissipating Heat of Optical Engine (17896249)
- 1.33 PELLICLE FOR AN EUV LITHOGRAPHY MASK AND A METHOD OF MANUFACTURING THEREOF (18232674)
- 1.34 EUV Lithography Mask With A Porous Reflective Multilayer Structure (18366136)
- 1.35 PHOTOMASK ASSEMBLY AND METHOD OF FORMING THE SAME (18362046)
- 1.36 SUB-RESOLUTION ASSIST FEATURES (18447425)
- 1.37 PHOTORESIST COMPOSITION AND METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE (18232264)
- 1.38 PHOTORESIST MATERIALS AND ASSOCIATED METHODS (18447568)
- 1.39 PHOTORESIST COMPOSITION AND METHOD OF FORMING PHOTORESIST PATTERN (18232225)
- 1.40 Polymer Layer in Semiconductor Device and Method of Manufacture (18446562)
- 1.41 PHOTORESIST COMPOSITION AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE (18232220)
- 1.42 UNDERLAYER COMPOSITION AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE (18232774)
- 1.43 PHOTORESIST UNDER-LAYER AND METHOD OF FORMING PHOTORESIST PATTERN (18232717)
- 1.44 SYSTEM AND METHOD FOR SUPPLYING AND DISPENSING BUBBLE-FREE PHOTOLITHOGRAPHY CHEMICAL SOLUTIONS (18365529)
- 1.45 APPARATUS, SYSTEM AND METHOD (18447104)
- 1.46 PHOTORESIST WITH POLAR-ACID-LABILE-GROUP (18447441)
- 1.47 METHOD FOR REMOVING RESISTOR LAYER, AND METHOD OF MANUFACTURING SEMICONDUCTOR (18358904)
- 1.48 SEMICONDUCTOR PROCESSING TOOL AND METHODS OF OPERATION (18446870)
- 1.49 OPTIMIZED MASK STITCHING (18231070)
- 1.50 OPTICAL PROXIMITY CORRECTION AND PHOTOMASKS (18361879)
- 1.51 ENHANCING LITHOGRAPHY OPERATION FOR MANUFACTURING SEMICONDUCTOR DEVICES (18232745)
- 1.52 MODULE VESSEL WITH SCRUBBER GUTTERS SIZED TO PREVENT OVERFLOW (18447361)
- 1.53 SEMICONDUCTOR WAFER COOLING (18362037)
- 1.54 MEMORY ADDRESS PROTECTION CIRCUIT AND METHOD OF OPERATING SAME (18355222)
- 1.55 FAULT DIAGNOSTICS (18303219)
- 1.56 METHOD AND SYSTEM FOR SEMICONDUCTOR WAFER DEFECT REVIEW (18447170)
- 1.57 INTEGRATED CIRCUIT AND METHOD OF FORMING THE SAME (17821559)
- 1.58 METHOD FOR CHIP INTEGRATION (17828648)
- 1.59 SEMICONDUCTOR DEVICE (18361815)
- 1.60 ANTI-FUSE ARRAY (18446684)
- 1.61 INTEGRATED CIRCUIT AND METHOD OF MANUFACTURING THE SAME (18446771)
- 1.62 METHOD OF GENERATING NETLIST INCLUDING PROXIMITY-EFFECT-INDUCER (PEI) PARAMETERS (18447964)
- 1.63 SILICON PHOTONICS SYSTEM (18155980)
- 1.64 INTEGRATED CIRCUIT AND METHOD OF FORMING THE SAME (18354377)
- 1.65 TRANSMISSION GATE STRUCTURE (18362195)
- 1.66 DESIGN RULE CHECK VIOLATION PREDICTION SYSTEMS AND METHODS (18446745)
- 1.67 DESIGN RULE CHECK VIOLATION PREDICTION SYSTEMS AND METHODS (18447455)
- 1.68 SYSTEM AND METHOD FOR GENERATING LAYOUT DIAGRAM INCLUDING WIRING ARRANGEMENT (18448143)
- 1.69 METHOD AND APPARATUS FOR DEFECT-TOLERANT MEMORY-BASED ARTIFICIAL NEURAL NETWORK (18231769)
- 1.70 NEUROMORPHIC COMPUTING DEVICE WITH THREE-DIMENSIONAL MEMORY (17824306)
- 1.71 CIRCUITS AND METHODS FOR COMPENSATING A MISMATCH IN A SENSE AMPLIFIER (18232768)
- 1.72 MEMORY DEVICE WITH SOURCE LINE CONTROL (18232542)
- 1.73 Systems and Methods for Controlling Power Management Operations in a Memory Device (18446818)
- 1.74 ARRANGEMENTS OF MEMORY DEVICES AND METHODS OF OPERATING THE MEMORY DEVICES (18446072)
- 1.75 FIRST FIRE OPERATION FOR OVONIC THRESHOLD SWITCH SELECTOR (17826180)
- 1.76 MEMORY DEVICE WITH REDUCED AREA (17752662)
- 1.77 THREE-DIMENSIONAL ONE TIME PROGRAMMABLE MEMORY (18232539)
- 1.78 NON-VOLATILE MEMORY CIRCUIT AND METHOD (18448152)
- 1.79 REPELLENT ELECTRODE FOR ELECTRON REPELLING (18448026)
- 1.80 ATOM PROBE TOMOGRAPHY SPECIMEN PREPARATION (18448014)
- 1.81 FOCUS RING FOR A PLASMA-BASED SEMICONDUCTOR PROCESSING TOOL (18447410)
- 1.82 DEVICE FOR ADJUSTING POSITION OF CHAMBER AND PLASMA PROCESS CHAMBER INCLUDING THE SAME FOR SEMICONDUCTOR MANUFACTURING (18231165)
- 1.83 SYSTEM AND METHOD FOR PARTICLE CONTROL IN MRAM PROCESSING (18231740)
- 1.84 SYSTEM AND METHOD FOR RESIDUAL GAS ANALYSIS (18361767)
- 1.85 SYSTEM AND METHOD FOR RESIDUAL GAS ANALYSIS (18361771)
- 1.86 SEMICONDUCTOR TOOL FOR COPPER DEPOSITION (18447557)
- 1.87 METHOD FOR REDUCING CHARGING OF SEMICONDUCTOR WAFERS (18225576)
- 1.88 INTERCONNECT STRUCTURE FOR SEMICONDUCTOR DEVICES (18359552)
- 1.89 SEMICONDUCTOR DEVICE PRE-CLEANING (17804447)
- 1.90 APPARATUS FOR ELECTRO-CHEMICAL PLATING (18231196)
- 1.91 Forming Low-Stress Silicon Nitride Layer Through Hydrogen Treatment (18358508)
- 1.92 SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURE (18446953)
- 1.93 PRE-TREATMENT APPARATUS (18188929)
- 1.94 DEVICE AND METHOD FOR HIGH PRESSURE ANNEAL (18365517)
- 1.95 SYSTEM AND METHOD FOR MULTIPLE STEP DIRECTIONAL PATTERNING (18447869)
- 1.96 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES (17829154)
- 1.97 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES (18232758)
- 1.98 EUV PHOTOMASK AND RELATED METHODS (18366397)
- 1.99 Method of Forming a Semiconductor Device by Driving Hydrogen into a Dielectric Layer from Another Dielectric Layer (18358609)
- 1.100 SURFACE OXIDATION CONTROL OF METAL GATES USING CAPPING LAYER (18230712)
- 1.101 AMBIENT CONTROLLED TWO-STEP THERMAL TREATMENT FOR SPIN-ON COATING LAYER PLANARIZATION (18446416)
- 1.102 Plasma-Assisted Etching Of Metal Oxides (18447943)
- 1.103 METHODS FOR FORMING POLYCRYSTALLINE CHANNEL ON DIELECTRIC FILMS WITH CONTROLLED GRAIN BOUNDARIES (18446415)
- 1.104 METHOD FOR IMPROVED POLYSILICON ETCH DIMENSIONAL CONTROL (18447810)
- 1.105 NITRIDE-CONTAINING STI LINER FOR SIGE CHANNEL (18446652)
- 1.106 SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURE (18447389)
- 1.107 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE (18447409)
- 1.108 SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING (18447443)
- 1.109 STACKED SEMICONDUCTOR DEVICES AND METHODS OF FORMING SAME (18447460)
- 1.110 Semiconductor Package and Method of Forming Thereof (18447428)
- 1.111 CHEMICAL DISPENSING SYSTEM (18447353)
- 1.112 UNDER BOAT SUPPORT WITH ELECTROSTATIC DISCHARGE STRUCTURE (18162538)
- 1.113 SYSTEMS AND METHODS FOR AIR FLOW OPTIMIZATION IN ENVIRONMENT FOR SEMICONDUCTOR DEVICE (18358517)
- 1.114 SEMICONDUCTOR PROCESSING METHOD AND APPARATUS (18447519)
- 1.115 SYSTEM AND METHOD FOR RING FRAME CLEANING AND INSPECTION (18231751)
- 1.116 SEMICONDUCTOR STRUCTURE AND FORMING METHOD THEREOF (18446549)
- 1.117 ETCH METHOD FOR INTERCONNECT STRUCTURE (18447134)
- 1.118 LOCAL INTERCONNECT (18447549)
- 1.119 SEMICONDUCTOR DEVICE STRUCTURE HAVING AIR GAP AND METHODS OF FORMING THE SAME (18230338)
- 1.120 FINFET STRUCTURE WITH CONTROLLED AIR GAPS (18360617)
- 1.121 Semiconductor Device with Air Gaps and Method of Fabrication Thereof (18446183)
- 1.122 Integrated Circuit Package and Method (18446521)
- 1.123 Semiconductor Package Including Step Seal Ring and Methods Forming Same (17819341)
- 1.124 Methods of Performing Chemical-Mechanical Polishing Process in Semiconductor Devices (18359486)
- 1.125 IMPROVED CONTACT RESISTANCE BETWEEN VIA AND CONDUCTIVE LINE (18447084)
- 1.126 Contact Structure For Semiconductor Device (18232718)
- 1.127 SOURCE/DRAIN CONTACT FORMATION METHODS AND DEVICES (18361770)
- 1.128 METHODS OF FORMING SEMICONDUCTOR DEVICE STRUCTURES (17825307)
- 1.129 METHOD FOR FORMING A CONTACT PLUG BY BOTTOM-UP METAL GROWTH (17825678)
- 1.130 GATE CONTACT STRUCTURE (18446326)
- 1.131 METHOD OF FORMING CONTACT METAL (18360587)
- 1.132 SEMICONDUCTOR PACKAGE AND METHOD COMPRISING FORMATION OF REDISTRIBUTION STRUCTURE AND INTERCONNECTING DIE (18446748)
- 1.133 METAL GATE PROCESS AND RELATED STRUCTURE (17804146)
- 1.134 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE (18446728)
- 1.135 METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE HAVING A DUMMY SECTION (18360814)
- 1.136 FinFETs With Epitaxy Regions Having Mixed Wavy and Non-Wavy Portions (18361354)
- 1.137 Semiconductor Device With Isolation Structures (18232171)
- 1.138 Semiconductor Device and Method of Manufacture (18363945)
- 1.139 Local Gate Height Tuning by CMP and Dummy Gate Design (18365405)
- 1.140 METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE (18361501)
- 1.141 MULTI-LAYERED INSULATING FILM STACK (18363439)
- 1.142 SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF (18447125)
- 1.143 Self-Aligned Structure For Semiconductor Devices (18447922)
- 1.144 SEMICONDUCTOR DEVICE STRUCTURE WITH SOURCE/DRAIN STRUCTURE AND METHOD FOR FORMING THE SAME (17824249)
- 1.145 Dual Channel Gate All Around Transistor Device and Fabrication Methods Thereof (18366562)
- 1.146 REPLACEMENT GATE PROCESS FOR SEMICONDUCTOR DEVICES (18359747)
- 1.147 HIGH-K DIELECTRIC MATERIALS WITH DIPOLE LAYER (18447239)
- 1.148 METHOD FOR FORMING SEMICONDUCTOR STRUCTURE (17824263)
- 1.149 MANUFACTURING PROCESS WITH ATOMIC LEVEL INSPECTION (18359206)
- 1.150 DEPOSITION SYSTEM AND METHOD (18361729)
- 1.151 SYSTEMS AND METHODS OF TESTING MEMORY DEVICES (18232518)
- 1.152 SEMICONDUCTOR PACKAGE INCLUDING TEST LINE STRUCTURE (18232520)
- 1.153 SEMICONDUCTOR DEVICE AND METHOD (18446591)
- 1.154 Package and Method for Forming the Same (17828691)
- 1.155 SEMICONDUCTOR PACKAGE AND METHOD OF FORMING SAME (18447416)
- 1.156 MANUFACTURING METHOD OF SEMICONDUCTOR PACKAGE (18363742)
- 1.157 STACKED SEMICONDUCTOR DEVICE INCLUDING A COOLING STRUCTURE (18446076)
- 1.158 SEMICONDUCTOR DEVICE HAVING A THERMAL CONTACT AND METHOD OF MAKING (18447927)
- 1.159 SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF (17827992)
- 1.160 INVERTED TRAPEZOIDAL HEAT DISSIPATING SOLDER STRUCTURE AND METHOD OF MAKING THE SAME (17829243)
- 1.161 VIA CONNECTION STRUCTURE HAVING MULTIPLE VIA TO VIA CONNECTIONS (17825336)
- 1.162 Through-Circuit Vias In Interconnect Structures (18232200)
- 1.163 SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF (18361917)
- 1.164 PACKAGE STRUCTURE AND METHOD OF FORMING THE SAME (18446146)
- 1.165 Semiconductor Device Having Backside Interconnect Structure on Through Substrate Via (18447871)
- 1.166 SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF (18359864)
- 1.167 Semiconductor Device and Method of Manufacture (18446006)
- 1.168 SEMICONDUCTOR PACKAGE DIELECTRIC SUSBTRATE INCLUDING A TRENCH (18232523)
- 1.169 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF (18363766)
- 1.170 Semiconductor Devices Including Decoupling Capacitors (18446648)
- 1.171 SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF (18446873)
- 1.172 BACK-END-OF-LINE PASSIVE DEVICE STRUCTURE (18447722)
- 1.173 SEMICONDUCTOR DEVICES WITH REDUCED EFFECT OF CAPACITIVE COUPLING (17825698)
- 1.174 SOURCE/DRAIN ISOLATION STRUCTURE, LAYOUT, AND METHOD (17752704)
- 1.175 Functional Component Within Interconnect Structure of Semiconductor Device and Method of Forming Same (18366771)
- 1.176 CONDUCTIVE RAIL STRUCTURE FOR SEMICONDUCTOR DEVICES (18447664)
- 1.177 DIAGONAL VIA STRUCTURE (18448125)
- 1.178 DUAL-MODE WIRELESS CHARGING DEVICE (18232312)
- 1.179 SEMICONDUCTOR DEVICE INCLUDING BACK SIDE POWER SUPPLY CIRCUIT (18232306)
- 1.180 ADVANCED NODE INTERCONNECT ROUTING METHODOLOGY (18446025)
- 1.181 Semiconductor Structures And Methods Of Forming The Same (18446113)
- 1.182 FIRST METAL STRUCTURE, LAYOUT, AND METHOD (17752737)
- 1.183 Semiconductor Devices Including Backside Power Via and Methods of Forming the Same (17819679)
- 1.184 POWER RAIL AND SIGNAL LINE ARRANGEMENT IN INTEGRATED CIRCUITS HAVING STACKED TRANSISTORS (18361666)
- 1.185 METHOD OF MANUFACTURING INTEGRATED CIRCUIT (18447572)
- 1.186 CELL STRUCTURE WITH INTERMEDIATE METAL LAYERS FOR POWER SUPPLIES (18448005)
- 1.187 METHOD OF MAKING SEMICONDUCTOR DEVICE INCLUDING BURIED CONDUCTIVE FINGERS (18448028)
- 1.188 Liner-Free Conductive Structures With Anchor Points (18232722)
- 1.189 GRAPHENE LAYER FOR REDUCED CONTACT RESISTANCE (18359383)
- 1.190 INTEGRATED CHIP WITH GRAPHENE BASED INTERCONNECT (18360012)
- 1.191 INTERCONNECT STRUCTURE INCLUDING CHARGED DIELECTRIC LAYERS (17825345)
- 1.192 SEMICONDUCTOR DEVICE INCLUDING INTERCONNECTS WITH LOWER CONTACT RESISTANCE (17825741)
- 1.193 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF (18446753)
- 1.194 DUAL-SIDED ROUTING IN 3D SIP STRUCTURE (18447769)
- 1.195 SEMICONDUCTOR PACKAGE DEVICE AND SEMICONDUCTOR WIRING SUBSTRATE THEREOF (17823063)
- 1.196 SEMICONDUCTOR PACKAGE CROSSTALK REDUCTION (17824353)
- 1.197 Semiconductor Devices With Backside Power Distribution Network And Frontside Through Silicon Via (18232713)
- 1.198 SEMICONDUCTOR DEVICE AND METHOD OF MAKING THE SAME (18230999)
- 1.199 SEMICONDCUTOR PACKAGES AND METHODS OF FORMING THEREOF (17881128)
- 1.200 Antenna Apparatus and Method (18366282)
- 1.201 POLYIMIDE PROFILE CONTROL (18446834)
- 1.202 BONDING STRUCTURES OF INTEGRATED CIRCUIT DEVICES AND METHOD FORMING THE SAME (18446028)
- 1.203 INTEGRATED CIRCUIT PACKAGE AND METHOD (18365362)
- 1.204 SEMICONDUCTOR DIE PACKAGE AND METHOD OF MANUFACTURE (18446732)
- 1.205 INTEGRATED CIRCUIT PACKAGE AND METHOD OF FORMING SAME (17664689)
- 1.206 Storage Layers For Wafer Bonding (18447968)
- 1.207 System and Method for Bonding Semiconductor Devices (18359416)
- 1.208 SEMICONDUCTOR STRUCTURE WITH INTEGRATED PASSIVE DEVICE HAVING OPPOSED SOLDER BUMPS (17824330)
- 1.209 SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF (18361953)
- 1.210 System Formed Through Package-In-Package Formation (18362649)
- 1.211 Semiconductor Devices and Methods of Manufacturing (18446291)
- 1.212 Integrated Circuit Packages and Methods of Forming the Same (17828310)
- 1.213 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE HAVING STAGGERED GATE-STUB-SIZE PROFILE AND SYSTEM FOR SAME (18447979)
- 1.214 Stacked Semiconductor Device and Method (18359578)
- 1.215 SEMICONDUCTOR DEVICE (18362030)
- 1.216 INTEGRATED CIRCUIT WITH BACKSIDE TRENCH FOR METAL GATE DEFINITION (18447881)
- 1.217 Profile Control Of Gate Structures In Semiconductor Devices (18232181)
- 1.218 Semiconductor Device and Method (18359492)
- 1.219 FIN END ISOLATION STRUCTURE FOR SEMICONDUCTOR DEVICES (18360007)
- 1.220 Semiconductor Devices Having Gate Dielectric Layers of Varying Thicknesses and Methods of Forming the Same (18360166)
- 1.221 Backside Power Rail And Methods Of Forming The Same (18360895)
- 1.222 SEMICONDUCTOR DEVICE STRUCTURE WITH AIR GAP AND METHOD FOR FORMING THE SAME (17826604)
- 1.223 SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAME (18229682)
- 1.224 Multi-Gate Device Integration with Separated Fin-Like Field Effect Transistor Cells and Gate-All-Around Transistor Cells (18360118)
- 1.225 SEMICONDUCTOR DEVICES WITH DIELECTRIC FINS AND METHOD FOR FORMING THE SAME (18361704)
- 1.226 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF (18362862)
- 1.227 SEMICONDUCTOR DEVICE AND METHOD (18365391)
- 1.228 SEMICONDUCTOR STRUCTURE WITH SELF-ALIGNED BACKSIDE POWER RAIL (18366004)
- 1.229 INTEGRATED CIRCUIT AND METHOD OF FORMING THE SAME (17828981)
- 1.230 INTEGRATED CIRCUIT WITH ACTIVE REGION JOGS (18362868)
- 1.231 LOW-COST SEMICONDUCTOR-ON-INSULATOR (SOI) STRUCTURE (18366831)
- 1.232 METAL GRID STRUCTURE TO IMPROVE IMAGE SENSOR PERFORMANCE (18360214)
- 1.233 IMAGE SENSOR WITH A HIGH ABSORPTION LAYER (18364662)
- 1.234 PIXEL SENSOR INCLUDING A TRANSFER FINFET (18447340)
- 1.235 EMBEDDED LIGHT SHIELD STRUCTURE FOR CMOS IMAGE SENSOR (18364667)
- 1.236 IMAGE SENSOR WITH PASSIVATION LAYER FOR DARK CURRENT REDUCTION (18446572)
- 1.237 METHOD FOR FORMING LIGHT PIPE STRUCTURE WITH HIGH QUANTUM EFFICIENCY (18360966)
- 1.238 OPTICAL BIOSENSOR DEVICE WITH OPTICAL SIGNAL ENHANCEMENT STRUCTURE (17824183)
- 1.239 IMAGE SENSOR DEVICE (18362866)
- 1.240 BACK-SIDE DEEP TRENCH ISOLATION STRUCTURE FOR IMAGE SENSOR (18364682)
- 1.241 DEEP TRENCH ISOLATION STRUCTURE IN A PIXEL SENSOR (18364734)
- 1.242 Anchor Structures And Methods For Uniform Wafer Planarization And Bonding (18232751)
- 1.243 SYSTEMS AND METHODS FOR SHIELDED INDUCTIVE DEVICES (18232332)
- 1.244 INDUCTIVE DEVICE (18447482)
- 1.245 Resistor Structure (18358557)
- 1.246 A MULTI-LAYERED RESISTOR WITH A TIGHT TEMPERATURE COEFFICIENT OF RESISTANCE TOLERANCE (18366156)
- 1.247 HIGH DENSITY METAL INSULATOR METAL CAPACITOR (18231754)
- 1.248 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF (17824436)
- 1.249 SUPER JUNCTION STRUCTURE (18448013)
- 1.250 NOVEL SOI DEVICE STRUCTURE FOR ROBUST ISOLATION (18232545)
- 1.251 SOURCE/DRAIN SPACER WITH AIR GAP IN SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME (18366210)
- 1.252 SEMICONDUCTOR DEVICE WITH CORNER ISOLATION PROTECTION AND METHODS OF FORMING THE SAME (18446665)
- 1.253 SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME (17824329)
- 1.254 SEMICONDUCTOR DEVICE AND METHOD (18359695)
- 1.255 GALLIUM NITRIDE DRAIN STRUCTURES AND METHODS OF FORMING THE SAME (17804751)
- 1.256 EPITAXIAL SOURCE/DRAIN STRUCTURE WITH HIGH DOPANT CONCENTRATION (17824915)
- 1.257 INTEGRATION OF LOW AND HIGH VOLTAGE DEVICES ON SUBSTRATE (18363077)
- 1.258 SEMICONDUCTOR DEVICES AND METHODS FOR FABRICATION THEREOF (17752211)
- 1.259 Semiconductor Gate-All-Around Device (18360080)
- 1.260 SILICON-GERMANIUM FINS AND METHODS OF PROCESSING THE SAME IN FIELD-EFFECT TRANSISTORS (18447149)
- 1.261 PROCESS AND STRUCTURE FOR SOURCE/DRAIN CONTACTS (18361262)
- 1.262 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE (18447053)
- 1.263 SEMICONDUCTOR DEVICE AND METHOD (18447212)
- 1.264 SEMICONDUCTOR STRUCTURE WITH WRAPAROUND BACKSIDE AMORPHOUS LAYER (18446864)
- 1.265 SEMICONDUCTOR DEVICES WITH BACKSIDE VIA AND METHODS THEREOF (18360085)
- 1.266 SEMICONDUCTOR DEVICE INTERCONNECTS AND METHODS OF FORMATION (18447344)
- 1.267 CONTACT PLUG STRUCTURE OF SEMICONDUCTOR DEVICE AND METHOD OF FORMING SAME (18366469)
- 1.268 NOVEL STRUCTURE FOR METAL GATE ELECTRODE AND METHOD OF FABRICATION (18446567)
- 1.269 Interconnect Features With Sharp Corners and Method Forming Same (18366352)
- 1.270 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES AND SEMICONDUCTOR DEVICES (17752461)
- 1.271 NANO TRANSISTORS WITH SOURCE/DRAIN HAVING SIDE CONTACTS TO 2-D MATERIAL (18365995)
- 1.272 MULTIGATE DEVICE WITH AIR GAP SPACER AND BACKSIDE RAIL CONTACT AND METHOD OF FABRICATING THEREOF (18446151)
- 1.273 SEMICONDUCTOR DEVICE INCLUDING GRAPHENE BARRIER AND METHOD OF FORMING THE SAME (17825411)
- 1.274 SOURCE/DRAIN SILICIDE FOR MULTIGATE DEVICE PERFORMANCE AND METHOD OF FABRICATING THEREOF (18447183)
- 1.275 SCHOTTKY DIODE AND METHOD OF FABRICATION THEREOF (17804125)
- 1.276 Spacer Structures for Nano-Sheet-Based Devices (18446733)
- 1.277 PARTIAL METAL GRAIN SIZE CONTROL TO IMPROVE CMP LOADING EFFECT (18447685)
- 1.278 Gate Spacers In Semiconductor Devices (18232191)
- 1.279 METHODS OF FORMING GATE STRUCTURES WITH UNIFORM GATE LENGTH (18446958)
- 1.280 Semiconductor Device with Air-Spacer (18446190)
- 1.281 3D CAPACITOR AND METHOD OF MANUFACTURING SAME (18366596)
- 1.282 GATE PROFILE MODULATION FOR SEMICONDUCTOR DEVICE (17824690)
- 1.283 SELF-ALIGNED INNER SPACER ON GATE-ALL-AROUND STRUCTURE AND METHODS OF FORMING THE SAME (18359597)
- 1.284 TRANSISTOR ISOLATION STRUCTURES (18446674)
- 1.285 SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THEREOF (18446632)
- 1.286 CIRCUIT DEVICES WITH GATE SEALS (18447467)
- 1.287 TRANSISTOR SPACER STRUCTURES (18447680)
- 1.288 Optimized Proximity Profile for Strained Source/Drain Feature and Method of Fabricating Thereof (18446998)
- 1.289 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF (17826174)
- 1.290 Channel Structures For Semiconductor Devices (18232159)
- 1.291 Controlling Fin-Thinning Through Feedback (18361540)
- 1.292 Liner for A Bi-Layer Gate Helmet and the Fabrication Thereof (18365315)
- 1.293 Nanowire Stack GAA Device with Inner Spacer and Methods for Producing the Same (18366297)
- 1.294 STRUCTURE FOR REDUCING SOURCE/DRAIN CONTACT RESISTANCE AT WAFER BACKSIDE (18366370)
- 1.295 SEMICONDUCTOR DEVICE AND METHOD (18446905)
- 1.296 Isolation Structures Of Semiconductor Devices (18447953)
- 1.297 EPITAXIAL STRUCTURES FOR FIN-LIKE FIELD EFFECT TRANSISTORS (18359542)
- 1.298 METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE (18232289)
- 1.299 SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF (18232544)
- 1.300 SYSTEM AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES (18446738)
- 1.301 SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURE (18447489)
- 1.302 Method of Gap Filling for Semiconductor Device (18447618)
- 1.303 GATED METAL-INSULATOR-SEMICONDUCTOR (MIS) TUNNEL DIODE HAVING NEGATIVE TRANSCONDUCTANCE (18361758)
- 1.304 INTEGRATION OF P-CHANNEL AND N-CHANNEL E-FET III-V DEVICES WITH OPTIMIZATION OF DEVICE PERFORMANCE (18364679)
- 1.305 FERROELECTRIC FIELD EFFECT TRANSISTOR AND METHODS OF FORMING THE SAME (17827755)
- 1.306 SEMICONDUCTOR DEVICE AND METHOD (18447153)
- 1.307 DEVICES WITH STRAINED ISOLATION FEATURES (18446960)
- 1.308 SOURCE/DRAIN FEATURES WITH IMPROVED STRAIN PROPERTIES (18447483)
- 1.309 SPACER STRUCTURES FOR SEMICONDUCTOR DEVICES (18227712)
- 1.310 METHOD OF FABRICATING A SOURCE/DRAIN RECESS IN A SEMICONDUCTOR DEVICE (18446539)
- 1.311 SEMICONDUCTOR DEVICE WITH SELF-ALIGNED WAVY CONTACT PROFILE AND METHOD OF FORMING THE SAME (18447855)
- 1.312 HIGH-VOLTAGE SEMICONDUCTOR DEVICES AND METHODS OF FORMATION (17804438)
- 1.313 Ferroelectric Semiconductor Device and Method (18447453)
- 1.314 ISOLATION STRUCTURES AND METHODS OF FORMING THE SAME IN FIELD-EFFECT TRANSISTORS (18446664)
- 1.315 SEMICONDUCTOR DEVICE HAVING ISOLATION STRUCTURE TO REDUCE CURRENT LEAKAGE (17824669)
- 1.316 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME (17825516)
- 1.317 Semiconductor Device With Fish Bone Structure And Methods Of Forming The Same (18359280)
- 1.318 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME (18359690)
- 1.319 SEMICONDUCTOR DEVICE AND METHOD (18446918)
- 1.320 METHOD OF MAKING DECOUPLING CAPACITOR (18447194)
- 1.321 SEMICONDUCTOR DEVICE INCLUDING DEEP TRENCH CAPACITORS AND VIA CONTACTS (17827251)
- 1.322 DECOUPLING FINFET CAPACITORS (18358464)
- 1.323 VOLTAGE AMPLIFIER BASED ON CASCADED CHARGE PUMP BOOSTING (18446031)
- 1.324 CLOCK GATING CIRCUIT AND METHOD OF OPERATING THE SAME (18362916)
- 1.325 DATA RETENTION CIRCUIT AND METHOD (18363192)
- 1.326 Flip Flop Circuit (18366981)
- 1.327 SYSTEM AND SEMICONDUCTOR DEVICE THEREIN (17828834)
- 1.328 POST-DRIVER WITH LOW VOLTAGE OPERATION AND ELECTROSTATIC DISCHARGE PROTECTION (17828581)
- 1.329 Semiconductor Device Including a Level Shifter and Method of Mitigating a Delay Between Input and Output Signals (18446849)
- 1.330 Semiconductor Device Including a Level Shifter and Method of Mitigating a Delay Between Input and Output Signals (18447372)
- 1.331 Systems and Methods for Phase Locked Loop Realignment With Skew Cancellation (18446881)
- 1.332 Programmable Regulator Voltage Controlled Ring Oscillator (18366742)
- 1.333 Circuits and Methods for a Noise Shaping Analog To Digital Converter (18361949)
- 1.334 RADIO FREQUENCY SWITCH (18231772)
- 1.335 METHOD OF USING INTEGRATED TRANSMITTER AND RECEIVER FRONT END MODULE (18361816)
- 1.336 METHOD AND APPARATUS FOR LOGIC CELL-BASED PUF GENERATORS (18232336)
- 1.337 EUV LIGHT SOURCE AND APPARATUS FOR LITHOGRAPHY (18231017)
- 1.338 SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME (17826225)
- 1.339 IC INCLUDING STANDARD CELLS AND SRAM CELLS (18361185)
- 1.340 SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF (18446094)
- 1.341 STATIC RANDOM ACCESS MEMORY WITH PRE-CHARGE CIRCUIT (18446546)
- 1.342 MULTI-LAYER HIGH-K GATE DIELECTRIC STRUCTURE (18446593)
- 1.343 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF (17828123)
- 1.344 MEMORY DEVICES AND METHODS FOR OPERATING THE SAME (17752580)
- 1.345 MEMORY DEVICE WITH IMPROVED ANTI-FUSE READ CURRENT (18447638)
- 1.346 SEMICONDUCTOR MEMORY DEVICES AND METHODS OF MANUFACTURING THEREOF (18361249)
- 1.347 Polysilicon Removal In Word Line Contact Region Of Memory Devices (18447965)
- 1.348 MEMORY DEVICE AND MANUFACTURING METHOD THEREOF (18446582)
- 1.349 FERROELECTRIC-BASED MEMORY DEVICE AND METHOD OF FORMING THE SAME (18181229)
- 1.350 MEMORY DEVICES AND METHODS OF MANUFACTURING THEREOF (18361548)
- 1.351 THREE-DIMENSIONAL MEMORY DEVICE AND METHOD (18366740)
- 1.352 THREE-DIMENSIONAL MEMORY DEVICES AND METHODS OF MANUFACTURING THEREOF (18446894)
- 1.353 SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME (18358966)
- 1.354 Memory Array and Methods of Forming Same (18365068)
- 1.355 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE (18447495)
- 1.356 MEMORY CELL ISOLATION (17826100)
- 1.357 EMBEDDED BACKSIDE MEMORY ON A FIELD EFFECT TRANSISTOR (18446557)
- 1.358 Memory Device and Methods of Forming Same (18446586)
- 1.359 METHOD OF FORMING SEMICONDUCTOR MEMORY DEVICE (17825440)
- 1.360 METHOD OF MANUFACTURING SEMICONDUCTOR STRUCTURE (18448100)
- 1.361 SELF-ALIGNED ENCAPSULATION HARD MASK TO SEPARATE PHYSICALLY UNDER-ETCHED MTJ CELLS TO REDUCE CONDUCTIVE RE-DEPOSITION (18232027)
- 1.362 Metal/Dielectric/Metal Hybrid Hard Mask To Define Ultra-Large Height Top Electrode For Sub 60nm MRAM Devices (18361677)
- 1.363 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FORMING THE SAME (18361832)
- 1.364 MRAM Fabrication and Device (18447383)
- 1.365 MEMORY DEVICE AND METHOD OF FABRICATING THE SAME (17827998)
- 1.366 MAGNETIC MEMORY DEVICE AND MANUFACTURING METHOD THEREOF (17900892)
- 1.367 MEMORY DEVICE AND FABRICATION METHOD THEREOF (18446703)
- 1.368 SIDEWALL SPACER STRUCTURE FOR MEMORY CELL (18364697)
- 1.369 MAGNETIC TUNNEL JUNCTION STRUCTURES WITH PROTECTION OUTER LAYERS (18446398)
- 1.370 STRUCTURE AND METHOD FOR MRAM DEVICES (18446563)
- 1.371 MAGNETIC TUNNELING JUNCTION WITH SYNTHETIC FREE LAYER FOR SOT-MRAM (18447912)
- 1.372 SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURE (18447232)
- 1.373 MEMORY DEVICE STRUCTURE WITH DATA STORAGE ELEMENT (18358685)
- 1.374 METHODS OF FORMING MEMORY DEVICES (18363751)
Patent applications for Taiwan Semiconductor Manufacturing Company, Ltd. on November 30th, 2023
PARTICLE REMOVER AND METHOD (18448963)
Main Inventor
Wen-Hao Cheng
TRANSDUCER DEVICE AND METHOD OF MANUFACTURE (17752558)
Main Inventor
Chi-Yuan Shih
DEVICE FOR FORMING CONDUCTIVE POWDER (18447161)
Main Inventor
You-Hua CHOU
POLISHING METROLOGY (17898163)
Main Inventor
Chih Hung CHEN
CHEMICAL MECHANICAL POLISHING APPARATUS AND METHOD (18446842)
Main Inventor
Chun-Hsi Huang
SYSTEM AND METHOD FOR REMOVING DEBRIS DURING CHEMICAL MECHANICAL PLANARIZATION (18447211)
Main Inventor
Chun-Wei HSU
MICROELECTROMECHANICAL SYSTEMS DEVICE HAVING A MECHANICALLY ROBUST ANTI-STICTION/OUTGASSING STRUCTURE (18364702)
Main Inventor
Kuei-Sung Chang
MEMS MICROPHONE AND MEMS ACCELEROMETER ON A SINGLE SUBSTRATE (18446741)
Main Inventor
Chun-Wen Cheng
WIRE-BOND DAMPER FOR SHOCK ABSORPTION (18446740)
Main Inventor
Tsung-Lin Hsieh
DIELECTRIC PROTECTION LAYER CONFIGURED TO INCREASE PERFORMANCE OF MEMS DEVICE (17825225)
Main Inventor
Wen-Chuan Tai
SHUTTER DISC FOR A SEMICONDUCTOR PROCESSING TOOL (18447543)
Main Inventor
Yi-Lin WANG
STRUCTURES AND METHODS FOR PROCESSING A SEMICONDUCTOR SUBSTRATE (18446392)
Main Inventor
Ming-Yi SHEN
DEPOSITION SYSTEM AND METHOD (18447911)
Main Inventor
Wen-Hao CHENG
Apparatus and Method for Use with a Substrate Chamber (18447493)
Main Inventor
Li-Ting Wang
APPARATUS FOR STORING AND TRANSPORTING SEMICONDUCTOR ELEMENTS, AND METHOD OF MAKING THE SAME (18231763)
Main Inventor
Tse-Lun HSU
WAFER DRYING SYSTEM (18446858)
Main Inventor
Wei-Chun Hsu
TEMPERATURE SENSOR CIRCUITS AND CONTROL CIRCUITS AND METHOD FOR TEMPERATURE SENSOR CIRCUITS (18150772)
Main Inventor
Jaw-Juinn HORNG
TEMPERATURE SENSING BASED ON METAL RAILS WITH DIFFERENT THERMAL-RESISTANCE COEFFICIENTS (18170401)
Main Inventor
Szu-Lin Liu
CAPACITOR-BASED TEMPERATURE-SENSING DEVICE (18232329)
Main Inventor
Shih-Lien Linus LU
ON-LINE ANALYSIS SYSTEM AND METHOD FOR SPECIALTY GASSES (17752730)
Main Inventor
Chiang Jeh CHEN
IN-SITU APPARATUS FOR DETECTING ABNORMALITY IN PROCESS TUBE (18361777)
Main Inventor
Yu-Jen YANG
INTEGRATED BIOLOGICAL SENSING PLATFORM (18232318)
Main Inventor
Tsung-Tsun CHEN
On-Chip Heater (18232719)
Main Inventor
Tung-Tsun Chen
STRUCTURE AND PROCESS FOR PHOTONIC PACKAGES (18366758)
Main Inventor
Chen-Hua Yu
PACKAGED DEVICE WITH OPTICAL PATHWAY (18447560)
Main Inventor
Hsien-Wei Chen
METHOD OF FABRICATING SEMICONDUCTOR STRUCTURE (18362983)
Main Inventor
Feng-Wei KUO
FIBER TO CHIP COUPLER AND METHOD OF MAKING THE SAME (18448032)
Main Inventor
Chen-Hao HUANG
METHOD OF MAKING PHOTONIC DEVICE (18448046)
Main Inventor
Chien-Ying WU
METHOD OF USING FIBER TO CHIP COUPLER AND METHOD OF MAKING (18448095)
Main Inventor
Sui-Ying HSU
METHOD OF MAKING SEMICONDUCTOR DEVICE INCLUDING OPTICAL THROUGH VIA AND METHOD OF USING (18358790)
Main Inventor
Yu-Hao CHEN
STRUCTURES AND PROCESS FLOW FOR INTEGRATED PHOTONIC-ELECTRIC IC PACKAGE BY USING POLYMER WAVEGUIDE (18232317)
Main Inventor
Yu-Hao CHEN
Thermo-Electric Cooler for Dissipating Heat of Optical Engine (17896249)
Main Inventor
Hsing-Kuo Hsia
PELLICLE FOR AN EUV LITHOGRAPHY MASK AND A METHOD OF MANUFACTURING THEREOF (18232674)
Main Inventor
Yun-Yue LIN
EUV Lithography Mask With A Porous Reflective Multilayer Structure (18366136)
Main Inventor
Chih-Tsung Shih
PHOTOMASK ASSEMBLY AND METHOD OF FORMING THE SAME (18362046)
Main Inventor
Kuo-Hao LEE
SUB-RESOLUTION ASSIST FEATURES (18447425)
Main Inventor
Kenji Yamazoe
PHOTORESIST COMPOSITION AND METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE (18232264)
Main Inventor
An-Ren ZI
PHOTORESIST MATERIALS AND ASSOCIATED METHODS (18447568)
Main Inventor
Ming-Hui WENG
PHOTORESIST COMPOSITION AND METHOD OF FORMING PHOTORESIST PATTERN (18232225)
Main Inventor
An-Ren Zi
Polymer Layer in Semiconductor Device and Method of Manufacture (18446562)
Main Inventor
Sih-Hao Liao
PHOTORESIST COMPOSITION AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE (18232220)
Main Inventor
Yen-Hao CHEN
UNDERLAYER COMPOSITION AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE (18232774)
Main Inventor
Ming-Hui WENG
PHOTORESIST UNDER-LAYER AND METHOD OF FORMING PHOTORESIST PATTERN (18232717)
Main Inventor
An-Ren ZI
SYSTEM AND METHOD FOR SUPPLYING AND DISPENSING BUBBLE-FREE PHOTOLITHOGRAPHY CHEMICAL SOLUTIONS (18365529)
Main Inventor
Wen-Zhan Zhou
APPARATUS, SYSTEM AND METHOD (18447104)
Main Inventor
Po-Han Wang
PHOTORESIST WITH POLAR-ACID-LABILE-GROUP (18447441)
Main Inventor
An-Ren Zi
METHOD FOR REMOVING RESISTOR LAYER, AND METHOD OF MANUFACTURING SEMICONDUCTOR (18358904)
Main Inventor
Hung-Jui Kuo
SEMICONDUCTOR PROCESSING TOOL AND METHODS OF OPERATION (18446870)
Main Inventor
Kai-Chieh CHANG
OPTIMIZED MASK STITCHING (18231070)
Main Inventor
Sagar TRIVEDI
OPTICAL PROXIMITY CORRECTION AND PHOTOMASKS (18361879)
Main Inventor
Dong-Yo Jheng
ENHANCING LITHOGRAPHY OPERATION FOR MANUFACTURING SEMICONDUCTOR DEVICES (18232745)
Main Inventor
Yih-Chen SU
MODULE VESSEL WITH SCRUBBER GUTTERS SIZED TO PREVENT OVERFLOW (18447361)
Main Inventor
Chun-Kai CHANG
SEMICONDUCTOR WAFER COOLING (18362037)
Main Inventor
Yung-Yao LEE
MEMORY ADDRESS PROTECTION CIRCUIT AND METHOD OF OPERATING SAME (18355222)
Main Inventor
Saman M. I. ADHAM
FAULT DIAGNOSTICS (18303219)
Main Inventor
Sandeep Kumar Goel
METHOD AND SYSTEM FOR SEMICONDUCTOR WAFER DEFECT REVIEW (18447170)
Main Inventor
Chung-Pin CHOU
INTEGRATED CIRCUIT AND METHOD OF FORMING THE SAME (17821559)
Main Inventor
Johnny Chiahao LI
METHOD FOR CHIP INTEGRATION (17828648)
Main Inventor
Yung Feng Chang
SEMICONDUCTOR DEVICE (18361815)
Main Inventor
Yu-Jen CHEN
ANTI-FUSE ARRAY (18446684)
Main Inventor
Meng-Sheng CHANG
INTEGRATED CIRCUIT AND METHOD OF MANUFACTURING THE SAME (18446771)
Main Inventor
Yu-Jung CHANG
METHOD OF GENERATING NETLIST INCLUDING PROXIMITY-EFFECT-INDUCER (PEI) PARAMETERS (18447964)
Main Inventor
Yen-Pin CHEN
SILICON PHOTONICS SYSTEM (18155980)
Main Inventor
Feng-Wei KUO
INTEGRATED CIRCUIT AND METHOD OF FORMING THE SAME (18354377)
Main Inventor
John LIN
TRANSMISSION GATE STRUCTURE (18362195)
Main Inventor
Shao-Lun CHIEN
DESIGN RULE CHECK VIOLATION PREDICTION SYSTEMS AND METHODS (18446745)
Main Inventor
Yi-Lin CHUANG
DESIGN RULE CHECK VIOLATION PREDICTION SYSTEMS AND METHODS (18447455)
Main Inventor
Yi-Lin CHUANG
SYSTEM AND METHOD FOR GENERATING LAYOUT DIAGRAM INCLUDING WIRING ARRANGEMENT (18448143)
Main Inventor
Fong-Yuan CHANG
METHOD AND APPARATUS FOR DEFECT-TOLERANT MEMORY-BASED ARTIFICIAL NEURAL NETWORK (18231769)
Main Inventor
Win-San KHWA
NEUROMORPHIC COMPUTING DEVICE WITH THREE-DIMENSIONAL MEMORY (17824306)
Main Inventor
Chieh Lee
CIRCUITS AND METHODS FOR COMPENSATING A MISMATCH IN A SENSE AMPLIFIER (18232768)
Main Inventor
Ku-Feng LIN
MEMORY DEVICE WITH SOURCE LINE CONTROL (18232542)
Main Inventor
Perng-Fei Yuh
Systems and Methods for Controlling Power Management Operations in a Memory Device (18446818)
Main Inventor
Sanjeev Kumar Jain
ARRANGEMENTS OF MEMORY DEVICES AND METHODS OF OPERATING THE MEMORY DEVICES (18446072)
Main Inventor
Chien-Yuan Chen
FIRST FIRE OPERATION FOR OVONIC THRESHOLD SWITCH SELECTOR (17826180)
Main Inventor
Elia Ambrosi
MEMORY DEVICE WITH REDUCED AREA (17752662)
Main Inventor
Chun-Ying Lee
THREE-DIMENSIONAL ONE TIME PROGRAMMABLE MEMORY (18232539)
Main Inventor
Meng-Sheng Chang
NON-VOLATILE MEMORY CIRCUIT AND METHOD (18448152)
Main Inventor
Gu-Huan LI
REPELLENT ELECTRODE FOR ELECTRON REPELLING (18448026)
Main Inventor
Ching-Heng YEN
ATOM PROBE TOMOGRAPHY SPECIMEN PREPARATION (18448014)
Main Inventor
Shih-Wei HUNG
FOCUS RING FOR A PLASMA-BASED SEMICONDUCTOR PROCESSING TOOL (18447410)
Main Inventor
Sheng-Chieh HUANG
DEVICE FOR ADJUSTING POSITION OF CHAMBER AND PLASMA PROCESS CHAMBER INCLUDING THE SAME FOR SEMICONDUCTOR MANUFACTURING (18231165)
Main Inventor
Ming Che CHEN
SYSTEM AND METHOD FOR PARTICLE CONTROL IN MRAM PROCESSING (18231740)
Main Inventor
Tsung-Han Kuo
SYSTEM AND METHOD FOR RESIDUAL GAS ANALYSIS (18361767)
Main Inventor
Yen-Liang CHEN
SYSTEM AND METHOD FOR RESIDUAL GAS ANALYSIS (18361771)
Main Inventor
Yen-Liang CHEN
SEMICONDUCTOR TOOL FOR COPPER DEPOSITION (18447557)
Main Inventor
Chia-Hung TSAI
METHOD FOR REDUCING CHARGING OF SEMICONDUCTOR WAFERS (18225576)
Main Inventor
Wei-Lin CHANG
INTERCONNECT STRUCTURE FOR SEMICONDUCTOR DEVICES (18359552)
Main Inventor
Po-Chuan Wang
SEMICONDUCTOR DEVICE PRE-CLEANING (17804447)
Main Inventor
Yi-Hsiang CHAO
APPARATUS FOR ELECTRO-CHEMICAL PLATING (18231196)
Main Inventor
Kuo-Lung HOU
Forming Low-Stress Silicon Nitride Layer Through Hydrogen Treatment (18358508)
Main Inventor
Wei-Che Hsieh
SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURE (18446953)
Main Inventor
Chun-Yen Peng
PRE-TREATMENT APPARATUS (18188929)
Main Inventor
Chun-Hsiang WANG
DEVICE AND METHOD FOR HIGH PRESSURE ANNEAL (18365517)
Main Inventor
Szu-Ying Chen
SYSTEM AND METHOD FOR MULTIPLE STEP DIRECTIONAL PATTERNING (18447869)
Main Inventor
Chih-Kai YANG
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES (17829154)
Main Inventor
Po-Han LIN
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES (18232758)
Main Inventor
Chun-Wei LIAO
EUV PHOTOMASK AND RELATED METHODS (18366397)
Main Inventor
Chi-Hung LIAO
Method of Forming a Semiconductor Device by Driving Hydrogen into a Dielectric Layer from Another Dielectric Layer (18358609)
Main Inventor
Hongfa Luan
SURFACE OXIDATION CONTROL OF METAL GATES USING CAPPING LAYER (18230712)
Main Inventor
Pei-Yu Chou
AMBIENT CONTROLLED TWO-STEP THERMAL TREATMENT FOR SPIN-ON COATING LAYER PLANARIZATION (18446416)
Main Inventor
Chen-Fong TSAI
Plasma-Assisted Etching Of Metal Oxides (18447943)
Main Inventor
Chansyun David YANG
METHODS FOR FORMING POLYCRYSTALLINE CHANNEL ON DIELECTRIC FILMS WITH CONTROLLED GRAIN BOUNDARIES (18446415)
Main Inventor
Cheng-Hsien WU
METHOD FOR IMPROVED POLYSILICON ETCH DIMENSIONAL CONTROL (18447810)
Main Inventor
Yun-Jui HE
NITRIDE-CONTAINING STI LINER FOR SIGE CHANNEL (18446652)
Main Inventor
Ya-Wen Chiu
SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURE (18447389)
Main Inventor
Wei-Chih Chen
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE (18447409)
Main Inventor
Wei-Yu Chen
SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING (18447443)
Main Inventor
Po-Chen Lai
STACKED SEMICONDUCTOR DEVICES AND METHODS OF FORMING SAME (18447460)
Main Inventor
Hsien-Wei Chen
Semiconductor Package and Method of Forming Thereof (18447428)
Main Inventor
Jiun Yi Wu
CHEMICAL DISPENSING SYSTEM (18447353)
Main Inventor
Ming-Chieh HSU
UNDER BOAT SUPPORT WITH ELECTROSTATIC DISCHARGE STRUCTURE (18162538)
Main Inventor
Ying-Hao WANG
SYSTEMS AND METHODS FOR AIR FLOW OPTIMIZATION IN ENVIRONMENT FOR SEMICONDUCTOR DEVICE (18358517)
Main Inventor
Yi-Fam Shiu
SEMICONDUCTOR PROCESSING METHOD AND APPARATUS (18447519)
Main Inventor
Shuang-Shiuan DENG
SYSTEM AND METHOD FOR RING FRAME CLEANING AND INSPECTION (18231751)
Main Inventor
Chien-Fa Lee
SEMICONDUCTOR STRUCTURE AND FORMING METHOD THEREOF (18446549)
Main Inventor
Soon-Kang HUANG
ETCH METHOD FOR INTERCONNECT STRUCTURE (18447134)
Main Inventor
Chun-Cheng Chou
LOCAL INTERCONNECT (18447549)
Main Inventor
Cheng-Hsien Wu
SEMICONDUCTOR DEVICE STRUCTURE HAVING AIR GAP AND METHODS OF FORMING THE SAME (18230338)
Main Inventor
Ting-Ya LO
FINFET STRUCTURE WITH CONTROLLED AIR GAPS (18360617)
Main Inventor
Wen-Che Tsai
Semiconductor Device with Air Gaps and Method of Fabrication Thereof (18446183)
Main Inventor
Chia-Hao Chang
Integrated Circuit Package and Method (18446521)
Main Inventor
Ting-Chen Tseng
Semiconductor Package Including Step Seal Ring and Methods Forming Same (17819341)
Main Inventor
Sheng-Han Tsai
Methods of Performing Chemical-Mechanical Polishing Process in Semiconductor Devices (18359486)
Main Inventor
Shih-Kang Fu
IMPROVED CONTACT RESISTANCE BETWEEN VIA AND CONDUCTIVE LINE (18447084)
Main Inventor
Chun-Yuan Chen
Contact Structure For Semiconductor Device (18232718)
Main Inventor
Hsu-Kai CHANG
SOURCE/DRAIN CONTACT FORMATION METHODS AND DEVICES (18361770)
Main Inventor
Cheng-Wei Chang
METHODS OF FORMING SEMICONDUCTOR DEVICE STRUCTURES (17825307)
Main Inventor
Yu-Chen KO
METHOD FOR FORMING A CONTACT PLUG BY BOTTOM-UP METAL GROWTH (17825678)
Main Inventor
Chung-Liang CHENG
GATE CONTACT STRUCTURE (18446326)
Main Inventor
Cheng-Chi Chuang
METHOD OF FORMING CONTACT METAL (18360587)
Main Inventor
Chun-Hsien Huang
SEMICONDUCTOR PACKAGE AND METHOD COMPRISING FORMATION OF REDISTRIBUTION STRUCTURE AND INTERCONNECTING DIE (18446748)
Main Inventor
Jiun Yi Wu
METAL GATE PROCESS AND RELATED STRUCTURE (17804146)
Main Inventor
Chih-Lun LU
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE (18446728)
Main Inventor
Chan Syun David Yang
METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE HAVING A DUMMY SECTION (18360814)
Main Inventor
Osamu KOIKE
FinFETs With Epitaxy Regions Having Mixed Wavy and Non-Wavy Portions (18361354)
Main Inventor
Shahaji B. More
Semiconductor Device With Isolation Structures (18232171)
Main Inventor
Pei-Wei Lee
Semiconductor Device and Method of Manufacture (18363945)
Main Inventor
Chia-Ching Lee
Local Gate Height Tuning by CMP and Dummy Gate Design (18365405)
Main Inventor
Ming-Chang Wen
METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE (18361501)
Main Inventor
Chung-Ting KO
MULTI-LAYERED INSULATING FILM STACK (18363439)
Main Inventor
Chieh-Ping Wang
SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF (18447125)
Main Inventor
Shu-Uei Jang
Self-Aligned Structure For Semiconductor Devices (18447922)
Main Inventor
Kuo-Cheng CHIANG
SEMICONDUCTOR DEVICE STRUCTURE WITH SOURCE/DRAIN STRUCTURE AND METHOD FOR FORMING THE SAME (17824249)
Main Inventor
Ta-Chun LIN
Dual Channel Gate All Around Transistor Device and Fabrication Methods Thereof (18366562)
Main Inventor
Wei-Sheng Yun
REPLACEMENT GATE PROCESS FOR SEMICONDUCTOR DEVICES (18359747)
Main Inventor
Yu-Jen Shen
HIGH-K DIELECTRIC MATERIALS WITH DIPOLE LAYER (18447239)
Main Inventor
Huiching Chang
METHOD FOR FORMING SEMICONDUCTOR STRUCTURE (17824263)
Main Inventor
Chih-Hsin Yang
MANUFACTURING PROCESS WITH ATOMIC LEVEL INSPECTION (18359206)
Main Inventor
I-Che Lee
DEPOSITION SYSTEM AND METHOD (18361729)
Main Inventor
Wen-Hao CHENG
SYSTEMS AND METHODS OF TESTING MEMORY DEVICES (18232518)
Main Inventor
Meng-Han Lin
SEMICONDUCTOR PACKAGE INCLUDING TEST LINE STRUCTURE (18232520)
Main Inventor
Tsung-Yang Hsieh
SEMICONDUCTOR DEVICE AND METHOD (18446591)
Main Inventor
Yin-Jie Pan
Package and Method for Forming the Same (17828691)
Main Inventor
Yu-Sheng Lin
SEMICONDUCTOR PACKAGE AND METHOD OF FORMING SAME (18447416)
Main Inventor
Ting-Chen Tseng
MANUFACTURING METHOD OF SEMICONDUCTOR PACKAGE (18363742)
Main Inventor
Meng-Liang Lin
STACKED SEMICONDUCTOR DEVICE INCLUDING A COOLING STRUCTURE (18446076)
Main Inventor
Jen-Yuan CHANG
SEMICONDUCTOR DEVICE HAVING A THERMAL CONTACT AND METHOD OF MAKING (18447927)
Main Inventor
Jian WU
SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF (17827992)
Main Inventor
Wei-Ming Wang
INVERTED TRAPEZOIDAL HEAT DISSIPATING SOLDER STRUCTURE AND METHOD OF MAKING THE SAME (17829243)
Main Inventor
Chang-Jung HSUEH
VIA CONNECTION STRUCTURE HAVING MULTIPLE VIA TO VIA CONNECTIONS (17825336)
Main Inventor
Ting-Yu Yeh
Through-Circuit Vias In Interconnect Structures (18232200)
Main Inventor
Jian-Hong LIN
SEMICONDUCTOR PACKAGE AND MANUFACTURING METHOD THEREOF (18361917)
Main Inventor
Jen-Chun Liao
PACKAGE STRUCTURE AND METHOD OF FORMING THE SAME (18446146)
Main Inventor
Chen-Hua Yu
Semiconductor Device Having Backside Interconnect Structure on Through Substrate Via (18447871)
Main Inventor
Yung-Chi Lin
SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF (18359864)
Main Inventor
Ting-Yu Yeh
Semiconductor Device and Method of Manufacture (18446006)
Main Inventor
Jiun Yi Wu
SEMICONDUCTOR PACKAGE DIELECTRIC SUSBTRATE INCLUDING A TRENCH (18232523)
Main Inventor
Yueh-Ting Lin
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF (18363766)
Main Inventor
Chien-Hung Chen
Semiconductor Devices Including Decoupling Capacitors (18446648)
Main Inventor
Yu-Xuan Huang
SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF (18446873)
Main Inventor
Chung-Ting Lu
BACK-END-OF-LINE PASSIVE DEVICE STRUCTURE (18447722)
Main Inventor
Tsung-Chieh Hsiao
SEMICONDUCTOR DEVICES WITH REDUCED EFFECT OF CAPACITIVE COUPLING (17825698)
Main Inventor
Chih-Yu Lu
SOURCE/DRAIN ISOLATION STRUCTURE, LAYOUT, AND METHOD (17752704)
Main Inventor
Chi-Yu LU
Functional Component Within Interconnect Structure of Semiconductor Device and Method of Forming Same (18366771)
Main Inventor
Hsien-Wei Chen
CONDUCTIVE RAIL STRUCTURE FOR SEMICONDUCTOR DEVICES (18447664)
Main Inventor
Yi-Bo LIAO
DIAGONAL VIA STRUCTURE (18448125)
Main Inventor
Shih-Wei PENG
DUAL-MODE WIRELESS CHARGING DEVICE (18232312)
Main Inventor
Shih-Wei LIANG
SEMICONDUCTOR DEVICE INCLUDING BACK SIDE POWER SUPPLY CIRCUIT (18232306)
Main Inventor
Gerben DOORNBOS
ADVANCED NODE INTERCONNECT ROUTING METHODOLOGY (18446025)
Main Inventor
Shih-Wei Peng
Semiconductor Structures And Methods Of Forming The Same (18446113)
Main Inventor
Lin-Yu Huang
FIRST METAL STRUCTURE, LAYOUT, AND METHOD (17752737)
Main Inventor
Chi-Yu LU
Semiconductor Devices Including Backside Power Via and Methods of Forming the Same (17819679)
Main Inventor
Po-Hsien Cheng
POWER RAIL AND SIGNAL LINE ARRANGEMENT IN INTEGRATED CIRCUITS HAVING STACKED TRANSISTORS (18361666)
Main Inventor
Chih-Liang CHEN
METHOD OF MANUFACTURING INTEGRATED CIRCUIT (18447572)
Main Inventor
Chih-Yu LAI
CELL STRUCTURE WITH INTERMEDIATE METAL LAYERS FOR POWER SUPPLIES (18448005)
Main Inventor
Li-Chun Tien
METHOD OF MAKING SEMICONDUCTOR DEVICE INCLUDING BURIED CONDUCTIVE FINGERS (18448028)
Main Inventor
Chih-Liang CHEN
Liner-Free Conductive Structures With Anchor Points (18232722)
Main Inventor
Hsu-Kai Chang
GRAPHENE LAYER FOR REDUCED CONTACT RESISTANCE (18359383)
Main Inventor
Shin-Yi Yang
INTEGRATED CHIP WITH GRAPHENE BASED INTERCONNECT (18360012)
Main Inventor
Shin-Yi Yang
INTERCONNECT STRUCTURE INCLUDING CHARGED DIELECTRIC LAYERS (17825345)
Main Inventor
Chien Hung Liu
SEMICONDUCTOR DEVICE INCLUDING INTERCONNECTS WITH LOWER CONTACT RESISTANCE (17825741)
Main Inventor
Hsi-Wen TIEN
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF (18446753)
Main Inventor
Hung-Ming CHEN
DUAL-SIDED ROUTING IN 3D SIP STRUCTURE (18447769)
Main Inventor
Po-Hao Tsai
SEMICONDUCTOR PACKAGE DEVICE AND SEMICONDUCTOR WIRING SUBSTRATE THEREOF (17823063)
Main Inventor
Sheng-Fan YANG
SEMICONDUCTOR PACKAGE CROSSTALK REDUCTION (17824353)
Main Inventor
Shu-Chun Yang
Semiconductor Devices With Backside Power Distribution Network And Frontside Through Silicon Via (18232713)
Main Inventor
Kam-Tou SIO
SEMICONDUCTOR DEVICE AND METHOD OF MAKING THE SAME (18230999)
Main Inventor
Cheng-Chieh HSIEH
SEMICONDCUTOR PACKAGES AND METHODS OF FORMING THEREOF (17881128)
Main Inventor
Sung-Yueh Wu
Antenna Apparatus and Method (18366282)
Main Inventor
Feng-Wei Kuo
POLYIMIDE PROFILE CONTROL (18446834)
Main Inventor
Chen-Chi HUANG
BONDING STRUCTURES OF INTEGRATED CIRCUIT DEVICES AND METHOD FORMING THE SAME (18446028)
Main Inventor
Chen-Yu Tsai
INTEGRATED CIRCUIT PACKAGE AND METHOD (18365362)
Main Inventor
Wen-Chih Chiou
SEMICONDUCTOR DIE PACKAGE AND METHOD OF MANUFACTURE (18446732)
Main Inventor
Kuan-Yu Huang
INTEGRATED CIRCUIT PACKAGE AND METHOD OF FORMING SAME (17664689)
Main Inventor
Yu-Sheng Lin
Storage Layers For Wafer Bonding (18447968)
Main Inventor
De-Yang CHIOU
System and Method for Bonding Semiconductor Devices (18359416)
Main Inventor
Kai-Tai Chang
SEMICONDUCTOR STRUCTURE WITH INTEGRATED PASSIVE DEVICE HAVING OPPOSED SOLDER BUMPS (17824330)
Main Inventor
Fong-yuan Chang
SEMICONDUCTOR STRUCTURE AND MANUFACTURING METHOD THEREOF (18361953)
Main Inventor
Chung-Liang CHENG
System Formed Through Package-In-Package Formation (18362649)
Main Inventor
Chen-Hua Yu
Semiconductor Devices and Methods of Manufacturing (18446291)
Main Inventor
Chang-Yi Yang
Integrated Circuit Packages and Methods of Forming the Same (17828310)
Main Inventor
Pei-Haw Tsao
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE HAVING STAGGERED GATE-STUB-SIZE PROFILE AND SYSTEM FOR SAME (18447979)
Main Inventor
Te-Hsin CHIU
Stacked Semiconductor Device and Method (18359578)
Main Inventor
Min-Feng Kao
SEMICONDUCTOR DEVICE (18362030)
Main Inventor
Chung-Te LIN
INTEGRATED CIRCUIT WITH BACKSIDE TRENCH FOR METAL GATE DEFINITION (18447881)
Main Inventor
Kuo-Cheng CHIANG
Profile Control Of Gate Structures In Semiconductor Devices (18232181)
Main Inventor
Kai-Chi WU
Semiconductor Device and Method (18359492)
Main Inventor
Jen-Chih Hsueh
FIN END ISOLATION STRUCTURE FOR SEMICONDUCTOR DEVICES (18360007)
Main Inventor
JHON JHY Liaw
Semiconductor Devices Having Gate Dielectric Layers of Varying Thicknesses and Methods of Forming the Same (18360166)
Main Inventor
Ta-Chun Lin
Backside Power Rail And Methods Of Forming The Same (18360895)
Main Inventor
Huan-Chieh Su
SEMICONDUCTOR DEVICE STRUCTURE WITH AIR GAP AND METHOD FOR FORMING THE SAME (17826604)
Main Inventor
Yi-Ruei JHAN
SEMICONDUCTOR DEVICE STRUCTURE AND METHODS OF FORMING THE SAME (18229682)
Main Inventor
Jui-Chien HUANG
Multi-Gate Device Integration with Separated Fin-Like Field Effect Transistor Cells and Gate-All-Around Transistor Cells (18360118)
Main Inventor
Jhon Jhy Liaw
SEMICONDUCTOR DEVICES WITH DIELECTRIC FINS AND METHOD FOR FORMING THE SAME (18361704)
Main Inventor
Kuan-Ting Pan
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF (18362862)
Main Inventor
Yu-Lien HUANG
SEMICONDUCTOR DEVICE AND METHOD (18365391)
Main Inventor
Shahaji B. More
SEMICONDUCTOR STRUCTURE WITH SELF-ALIGNED BACKSIDE POWER RAIL (18366004)
Main Inventor
Kuo-Cheng Chiang
INTEGRATED CIRCUIT AND METHOD OF FORMING THE SAME (17828981)
Main Inventor
Chin-Wei HSU
INTEGRATED CIRCUIT WITH ACTIVE REGION JOGS (18362868)
Main Inventor
Tian-Yu XIE
LOW-COST SEMICONDUCTOR-ON-INSULATOR (SOI) STRUCTURE (18366831)
Main Inventor
Harry-Hak-Lay Chuang
METAL GRID STRUCTURE TO IMPROVE IMAGE SENSOR PERFORMANCE (18360214)
Main Inventor
Ming Chyi Liu
IMAGE SENSOR WITH A HIGH ABSORPTION LAYER (18364662)
Main Inventor
Chien-Chang Huang
PIXEL SENSOR INCLUDING A TRANSFER FINFET (18447340)
Main Inventor
Feng-Chien HSIEH
EMBEDDED LIGHT SHIELD STRUCTURE FOR CMOS IMAGE SENSOR (18364667)
Main Inventor
Shih-Hsun Hsu
IMAGE SENSOR WITH PASSIVATION LAYER FOR DARK CURRENT REDUCTION (18446572)
Main Inventor
Hsiang-Lin Chen
METHOD FOR FORMING LIGHT PIPE STRUCTURE WITH HIGH QUANTUM EFFICIENCY (18360966)
Main Inventor
Tsun-Kai Tsao
OPTICAL BIOSENSOR DEVICE WITH OPTICAL SIGNAL ENHANCEMENT STRUCTURE (17824183)
Main Inventor
Yi-Hsien Chang
IMAGE SENSOR DEVICE (18362866)
Main Inventor
Yun-Wei CHENG
BACK-SIDE DEEP TRENCH ISOLATION STRUCTURE FOR IMAGE SENSOR (18364682)
Main Inventor
Cheng-Ta Wu
DEEP TRENCH ISOLATION STRUCTURE IN A PIXEL SENSOR (18364734)
Main Inventor
Feng-Chien HSIEH
Anchor Structures And Methods For Uniform Wafer Planarization And Bonding (18232751)
Main Inventor
Chia-Yu Wei
SYSTEMS AND METHODS FOR SHIELDED INDUCTIVE DEVICES (18232332)
Main Inventor
Feng Wei KUO
INDUCTIVE DEVICE (18447482)
Main Inventor
Wei-Yu CHOU
Resistor Structure (18358557)
Main Inventor
Chih-Fan Huang
A MULTI-LAYERED RESISTOR WITH A TIGHT TEMPERATURE COEFFICIENT OF RESISTANCE TOLERANCE (18366156)
Main Inventor
Szu-Hsien Lo
HIGH DENSITY METAL INSULATOR METAL CAPACITOR (18231754)
Main Inventor
Wei Kai SHIH
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF (17824436)
Main Inventor
Tsung-Chieh HSIAO
SUPER JUNCTION STRUCTURE (18448013)
Main Inventor
Shuai ZHANG
NOVEL SOI DEVICE STRUCTURE FOR ROBUST ISOLATION (18232545)
Main Inventor
Lin-Chen Lu
SOURCE/DRAIN SPACER WITH AIR GAP IN SEMICONDUCTOR DEVICES AND METHODS OF FABRICATING THE SAME (18366210)
Main Inventor
Ko-Cheng Liu
SEMICONDUCTOR DEVICE WITH CORNER ISOLATION PROTECTION AND METHODS OF FORMING THE SAME (18446665)
Main Inventor
Bwo-Ning Chen
SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME (17824329)
Main Inventor
Lin-Yu HUANG
SEMICONDUCTOR DEVICE AND METHOD (18359695)
Main Inventor
Hsin-Yi Lee
GALLIUM NITRIDE DRAIN STRUCTURES AND METHODS OF FORMING THE SAME (17804751)
Main Inventor
Chi-Ming CHEN
EPITAXIAL SOURCE/DRAIN STRUCTURE WITH HIGH DOPANT CONCENTRATION (17824915)
Main Inventor
Chih Sheng Huang
INTEGRATION OF LOW AND HIGH VOLTAGE DEVICES ON SUBSTRATE (18363077)
Main Inventor
Hsin Fu Lin
SEMICONDUCTOR DEVICES AND METHODS FOR FABRICATION THEREOF (17752211)
Main Inventor
Jui-Lin CHANG
Semiconductor Gate-All-Around Device (18360080)
Main Inventor
Jhon Jhy Liaw
SILICON-GERMANIUM FINS AND METHODS OF PROCESSING THE SAME IN FIELD-EFFECT TRANSISTORS (18447149)
Main Inventor
Yu-Shan Lu
PROCESS AND STRUCTURE FOR SOURCE/DRAIN CONTACTS (18361262)
Main Inventor
Meng-Huan Jao
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE (18447053)
Main Inventor
Chun-Hsien Huang
SEMICONDUCTOR DEVICE AND METHOD (18447212)
Main Inventor
Po-Chuan Wang
SEMICONDUCTOR STRUCTURE WITH WRAPAROUND BACKSIDE AMORPHOUS LAYER (18446864)
Main Inventor
Shih-Chuan Chiu
SEMICONDUCTOR DEVICES WITH BACKSIDE VIA AND METHODS THEREOF (18360085)
Main Inventor
Po-Yu Huang
SEMICONDUCTOR DEVICE INTERCONNECTS AND METHODS OF FORMATION (18447344)
Main Inventor
Te-Chih HSIUNG
CONTACT PLUG STRUCTURE OF SEMICONDUCTOR DEVICE AND METHOD OF FORMING SAME (18366469)
Main Inventor
Pei-Yu Chou
NOVEL STRUCTURE FOR METAL GATE ELECTRODE AND METHOD OF FABRICATION (18446567)
Main Inventor
Ru-Shang Hsiao
Interconnect Features With Sharp Corners and Method Forming Same (18366352)
Main Inventor
Tze-Liang Lee
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICES AND SEMICONDUCTOR DEVICES (17752461)
Main Inventor
Yung-Hsiang CHAN
NANO TRANSISTORS WITH SOURCE/DRAIN HAVING SIDE CONTACTS TO 2-D MATERIAL (18365995)
Main Inventor
Chao-Ching Cheng
MULTIGATE DEVICE WITH AIR GAP SPACER AND BACKSIDE RAIL CONTACT AND METHOD OF FABRICATING THEREOF (18446151)
Main Inventor
Guan-Lin CHEN
SEMICONDUCTOR DEVICE INCLUDING GRAPHENE BARRIER AND METHOD OF FORMING THE SAME (17825411)
Main Inventor
Shin-Yi YANG
SOURCE/DRAIN SILICIDE FOR MULTIGATE DEVICE PERFORMANCE AND METHOD OF FABRICATING THEREOF (18447183)
Main Inventor
Chih-Ching Wang
SCHOTTKY DIODE AND METHOD OF FABRICATION THEREOF (17804125)
Main Inventor
Wen-Shun LO
Spacer Structures for Nano-Sheet-Based Devices (18446733)
Main Inventor
Shih-Cheng Chen
PARTIAL METAL GRAIN SIZE CONTROL TO IMPROVE CMP LOADING EFFECT (18447685)
Main Inventor
Anhao CHENG
Gate Spacers In Semiconductor Devices (18232191)
Main Inventor
Wei-Liang LU
METHODS OF FORMING GATE STRUCTURES WITH UNIFORM GATE LENGTH (18446958)
Main Inventor
Shahaji B. More
Semiconductor Device with Air-Spacer (18446190)
Main Inventor
Wei-Yang Lee
3D CAPACITOR AND METHOD OF MANUFACTURING SAME (18366596)
Main Inventor
Chi-Wen LIU
GATE PROFILE MODULATION FOR SEMICONDUCTOR DEVICE (17824690)
Main Inventor
Tien-Shun CHANG
SELF-ALIGNED INNER SPACER ON GATE-ALL-AROUND STRUCTURE AND METHODS OF FORMING THE SAME (18359597)
Main Inventor
Tsungyu Hung
TRANSISTOR ISOLATION STRUCTURES (18446674)
Main Inventor
Mrunal Abhijith KHADERBAD
SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THEREOF (18446632)
Main Inventor
Chih-Hsuan Lin
CIRCUIT DEVICES WITH GATE SEALS (18447467)
Main Inventor
Sheng-Chou Lai
TRANSISTOR SPACER STRUCTURES (18447680)
Main Inventor
Chansyun David YANG
Optimized Proximity Profile for Strained Source/Drain Feature and Method of Fabricating Thereof (18446998)
Main Inventor
Chun-An Lin
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF (17826174)
Main Inventor
Wang-Chun Huang
Channel Structures For Semiconductor Devices (18232159)
Main Inventor
Ding-Kang SHIH
Controlling Fin-Thinning Through Feedback (18361540)
Main Inventor
Tsu-Hui Su
Liner for A Bi-Layer Gate Helmet and the Fabrication Thereof (18365315)
Main Inventor
Huan-Chieh Su
Nanowire Stack GAA Device with Inner Spacer and Methods for Producing the Same (18366297)
Main Inventor
Tzu-Chung Wang
STRUCTURE FOR REDUCING SOURCE/DRAIN CONTACT RESISTANCE AT WAFER BACKSIDE (18366370)
Main Inventor
Huan-Chieh Su
SEMICONDUCTOR DEVICE AND METHOD (18446905)
Main Inventor
Shahaji B. More
Isolation Structures Of Semiconductor Devices (18447953)
Main Inventor
Jia-Chuan You
EPITAXIAL STRUCTURES FOR FIN-LIKE FIELD EFFECT TRANSISTORS (18359542)
Main Inventor
Chia-Ta Yu
METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE AND A SEMICONDUCTOR DEVICE (18232289)
Main Inventor
Chia-Chi YU
SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF (18232544)
Main Inventor
Shih-Yao LIN
SYSTEM AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES (18446738)
Main Inventor
Chia-Ao Chang
SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURE (18447489)
Main Inventor
Wei-Chih KAO
Method of Gap Filling for Semiconductor Device (18447618)
Main Inventor
Te-Yang Lai
GATED METAL-INSULATOR-SEMICONDUCTOR (MIS) TUNNEL DIODE HAVING NEGATIVE TRANSCONDUCTANCE (18361758)
Main Inventor
Jenn-Gwo Hwu
INTEGRATION OF P-CHANNEL AND N-CHANNEL E-FET III-V DEVICES WITH OPTIMIZATION OF DEVICE PERFORMANCE (18364679)
Main Inventor
Man-Ho Kwan
FERROELECTRIC FIELD EFFECT TRANSISTOR AND METHODS OF FORMING THE SAME (17827755)
Main Inventor
Gerben Doornbos
SEMICONDUCTOR DEVICE AND METHOD (18447153)
Main Inventor
Bo-Feng Young
DEVICES WITH STRAINED ISOLATION FEATURES (18446960)
Main Inventor
Xusheng Wu
SOURCE/DRAIN FEATURES WITH IMPROVED STRAIN PROPERTIES (18447483)
Main Inventor
Chih-Ching Wang
SPACER STRUCTURES FOR SEMICONDUCTOR DEVICES (18227712)
Main Inventor
Cheng-Yi PENG
METHOD OF FABRICATING A SOURCE/DRAIN RECESS IN A SEMICONDUCTOR DEVICE (18446539)
Main Inventor
Eric PENG
SEMICONDUCTOR DEVICE WITH SELF-ALIGNED WAVY CONTACT PROFILE AND METHOD OF FORMING THE SAME (18447855)
Main Inventor
Chia-Ta Yu
HIGH-VOLTAGE SEMICONDUCTOR DEVICES AND METHODS OF FORMATION (17804438)
Main Inventor
Jhu-Min SONG
Ferroelectric Semiconductor Device and Method (18447453)
Main Inventor
Chia-Cheng Ho
ISOLATION STRUCTURES AND METHODS OF FORMING THE SAME IN FIELD-EFFECT TRANSISTORS (18446664)
Main Inventor
Shi Ning Ju
SEMICONDUCTOR DEVICE HAVING ISOLATION STRUCTURE TO REDUCE CURRENT LEAKAGE (17824669)
Main Inventor
Hung-Yu YEN
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME (17825516)
Main Inventor
Shuen-Shin LIANG
Semiconductor Device With Fish Bone Structure And Methods Of Forming The Same (18359280)
Main Inventor
Chih-Chuan Yang
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME (18359690)
Main Inventor
Marcus Johannes Henricus VAN DAL
SEMICONDUCTOR DEVICE AND METHOD (18446918)
Main Inventor
Chunchieh Wang
METHOD OF MAKING DECOUPLING CAPACITOR (18447194)
Main Inventor
Szu-Lin LIU
SEMICONDUCTOR DEVICE INCLUDING DEEP TRENCH CAPACITORS AND VIA CONTACTS (17827251)
Main Inventor
Po-Chia Lai
DECOUPLING FINFET CAPACITORS (18358464)
Main Inventor
Chung-Hui Chen
VOLTAGE AMPLIFIER BASED ON CASCADED CHARGE PUMP BOOSTING (18446031)
Main Inventor
Chin-Ho Chang
CLOCK GATING CIRCUIT AND METHOD OF OPERATING THE SAME (18362916)
Main Inventor
Seid Hadi RASOULI
DATA RETENTION CIRCUIT AND METHOD (18363192)
Main Inventor
Kai-Chi HUANG
Flip Flop Circuit (18366981)
Main Inventor
Po-Chia Lai
SYSTEM AND SEMICONDUCTOR DEVICE THEREIN (17828834)
Main Inventor
Tsung-Che LU
POST-DRIVER WITH LOW VOLTAGE OPERATION AND ELECTROSTATIC DISCHARGE PROTECTION (17828581)
Main Inventor
Chin-Hua Wen
Semiconductor Device Including a Level Shifter and Method of Mitigating a Delay Between Input and Output Signals (18446849)
Main Inventor
Jerrin Pathrose Vareed
Semiconductor Device Including a Level Shifter and Method of Mitigating a Delay Between Input and Output Signals (18447372)
Main Inventor
Jerrin Pathrose Vareed
Systems and Methods for Phase Locked Loop Realignment With Skew Cancellation (18446881)
Main Inventor
Tsung-Hsien Tsai
Programmable Regulator Voltage Controlled Ring Oscillator (18366742)
Main Inventor
Tsung-Hsien Tsai
Circuits and Methods for a Noise Shaping Analog To Digital Converter (18361949)
Main Inventor
Martin Kinyua
RADIO FREQUENCY SWITCH (18231772)
Main Inventor
Jun-De JIN
METHOD OF USING INTEGRATED TRANSMITTER AND RECEIVER FRONT END MODULE (18361816)
Main Inventor
En-Hsiang YEH
METHOD AND APPARATUS FOR LOGIC CELL-BASED PUF GENERATORS (18232336)
Main Inventor
Shih-Lien Linus LU
EUV LIGHT SOURCE AND APPARATUS FOR LITHOGRAPHY (18231017)
Main Inventor
Shang-Chieh CHIEN
SEMICONDUCTOR STRUCTURE AND METHOD FOR FORMING THE SAME (17826225)
Main Inventor
Chun-Hung CHEN
IC INCLUDING STANDARD CELLS AND SRAM CELLS (18361185)
Main Inventor
Jhon-Jhy LIAW
SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURING THEREOF (18446094)
Main Inventor
Shih-Yao Lin
STATIC RANDOM ACCESS MEMORY WITH PRE-CHARGE CIRCUIT (18446546)
Main Inventor
Po-Sheng WANG
MULTI-LAYER HIGH-K GATE DIELECTRIC STRUCTURE (18446593)
Main Inventor
Chih-Yu Hsu
SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF (17828123)
Main Inventor
Jhon-Jhy LIAW
MEMORY DEVICES AND METHODS FOR OPERATING THE SAME (17752580)
Main Inventor
Hsiang-Wei Liu
MEMORY DEVICE WITH IMPROVED ANTI-FUSE READ CURRENT (18447638)
Main Inventor
Meng-Sheng CHANG
SEMICONDUCTOR MEMORY DEVICES AND METHODS OF MANUFACTURING THEREOF (18361249)
Main Inventor
Meng-Han Lin
Polysilicon Removal In Word Line Contact Region Of Memory Devices (18447965)
Main Inventor
Yen-Jou WU
MEMORY DEVICE AND MANUFACTURING METHOD THEREOF (18446582)
Main Inventor
Feng-Ching Chu
FERROELECTRIC-BASED MEMORY DEVICE AND METHOD OF FORMING THE SAME (18181229)
Main Inventor
Yi-Hsuan Chen
MEMORY DEVICES AND METHODS OF MANUFACTURING THEREOF (18361548)
Main Inventor
Meng-Han Lin
THREE-DIMENSIONAL MEMORY DEVICE AND METHOD (18366740)
Main Inventor
Chia-Yu Ling
THREE-DIMENSIONAL MEMORY DEVICES AND METHODS OF MANUFACTURING THEREOF (18446894)
Main Inventor
Meng-Han Lin
SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME (18358966)
Main Inventor
Gerben Doornbos
Memory Array and Methods of Forming Same (18365068)
Main Inventor
Yu-Ming Lin
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE (18447495)
Main Inventor
Meng-Han Lin
MEMORY CELL ISOLATION (17826100)
Main Inventor
Tzu-Yu Chen
EMBEDDED BACKSIDE MEMORY ON A FIELD EFFECT TRANSISTOR (18446557)
Main Inventor
Kuan-Liang Liu
Memory Device and Methods of Forming Same (18446586)
Main Inventor
Chenchen Jacob Wang
METHOD OF FORMING SEMICONDUCTOR MEMORY DEVICE (17825440)
Main Inventor
Wei-Chih WEN
METHOD OF MANUFACTURING SEMICONDUCTOR STRUCTURE (18448100)
Main Inventor
Yu-Hao CHEN
SELF-ALIGNED ENCAPSULATION HARD MASK TO SEPARATE PHYSICALLY UNDER-ETCHED MTJ CELLS TO REDUCE CONDUCTIVE RE-DEPOSITION (18232027)
Main Inventor
Yi Yang
Metal/Dielectric/Metal Hybrid Hard Mask To Define Ultra-Large Height Top Electrode For Sub 60nm MRAM Devices (18361677)
Main Inventor
Yi Yang
SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FORMING THE SAME (18361832)
Main Inventor
Hsiang-Ku Shen
MRAM Fabrication and Device (18447383)
Main Inventor
Jung-Tang Wu
MEMORY DEVICE AND METHOD OF FABRICATING THE SAME (17827998)
Main Inventor
Yen-Lin Huang
MAGNETIC MEMORY DEVICE AND MANUFACTURING METHOD THEREOF (17900892)
Main Inventor
Ming-Yuan Song
MEMORY DEVICE AND FABRICATION METHOD THEREOF (18446703)
Main Inventor
Jun-Yao CHEN
SIDEWALL SPACER STRUCTURE FOR MEMORY CELL (18364697)
Main Inventor
Yao-Wen Chang
MAGNETIC TUNNEL JUNCTION STRUCTURES WITH PROTECTION OUTER LAYERS (18446398)
Main Inventor
Sheng-Chang CHEN
STRUCTURE AND METHOD FOR MRAM DEVICES (18446563)
Main Inventor
Tsung-Chieh Hsiao
MAGNETIC TUNNELING JUNCTION WITH SYNTHETIC FREE LAYER FOR SOT-MRAM (18447912)
Main Inventor
Chien-Min Lee
SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURE (18447232)
Main Inventor
Tung-Ying Lee
MEMORY DEVICE STRUCTURE WITH DATA STORAGE ELEMENT (18358685)
Main Inventor
Hai-Dang TRINH
METHODS OF FORMING MEMORY DEVICES (18363751)
Main Inventor
Hung-Li Chiang