Difference between revisions of "NANYA TECHNOLOGY CORPORATION patent applications published on November 30th, 2023"
Jump to navigation
Jump to search
Wikipatents (talk | contribs) |
Wikipatents (talk | contribs) (Creating a new page) |
||
Line 1: | Line 1: | ||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
− | |||
==Patent applications for NANYA TECHNOLOGY CORPORATION on November 30th, 2023== | ==Patent applications for NANYA TECHNOLOGY CORPORATION on November 30th, 2023== | ||
− | ===VOLTAGE REGULATOR FOR PROVIDING WORD LINE VOLTAGE ([[US Patent Application 17829350. VOLTAGE REGULATOR FOR PROVIDING WORD LINE VOLTAGE simplified abstract|17829350]])=== | + | ===VOLTAGE REGULATOR FOR PROVIDING WORD LINE VOLTAGE ([[US Patent Application 17829350. VOLTAGE REGULATOR FOR PROVIDING WORD LINE VOLTAGE simplified abstract (NANYA TECHNOLOGY CORPORATION)|17829350]])=== |
Line 33: | Line 9: | ||
− | ===MEMORY DEVICE HAVING PROTRUSION OF WORD LINE ([[US Patent Application 17824011. MEMORY DEVICE HAVING PROTRUSION OF WORD LINE simplified abstract|17824011]])=== | + | ===MEMORY DEVICE HAVING PROTRUSION OF WORD LINE ([[US Patent Application 17824011. MEMORY DEVICE HAVING PROTRUSION OF WORD LINE simplified abstract (NANYA TECHNOLOGY CORPORATION)|17824011]])=== |
Line 41: | Line 17: | ||
− | ===SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR PREPARING THE SAME ([[US Patent Application 18231912. SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR PREPARING THE SAME simplified abstract|18231912]])=== | + | ===SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR PREPARING THE SAME ([[US Patent Application 18231912. SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR PREPARING THE SAME simplified abstract (NANYA TECHNOLOGY CORPORATION)|18231912]])=== |
Line 49: | Line 25: | ||
− | ===METHOD OF PREPARING ACTIVE AREAS ([[US Patent Application 17828802. METHOD OF PREPARING ACTIVE AREAS simplified abstract|17828802]])=== | + | ===METHOD OF PREPARING ACTIVE AREAS ([[US Patent Application 17828802. METHOD OF PREPARING ACTIVE AREAS simplified abstract (NANYA TECHNOLOGY CORPORATION)|17828802]])=== |
Line 57: | Line 33: | ||
− | ===METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH CONTACT STRUCTURE ([[US Patent Application 17824481. METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH CONTACT STRUCTURE simplified abstract|17824481]])=== | + | ===METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH CONTACT STRUCTURE ([[US Patent Application 17824481. METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH CONTACT STRUCTURE simplified abstract (NANYA TECHNOLOGY CORPORATION)|17824481]])=== |
Line 65: | Line 41: | ||
− | ===METHOD FOR PREPARING SEMICONDUCTOR DEVICE WITH AIR SPACER ([[US Patent Application 18232833. METHOD FOR PREPARING SEMICONDUCTOR DEVICE WITH AIR SPACER simplified abstract|18232833]])=== | + | ===METHOD FOR PREPARING SEMICONDUCTOR DEVICE WITH AIR SPACER ([[US Patent Application 18232833. METHOD FOR PREPARING SEMICONDUCTOR DEVICE WITH AIR SPACER simplified abstract (NANYA TECHNOLOGY CORPORATION)|18232833]])=== |
Line 73: | Line 49: | ||
− | ===METHOD FOR PREPARING SEMICONDUCTOR DEVICE WITH AIR GAP ([[US Patent Application 18232937. METHOD FOR PREPARING SEMICONDUCTOR DEVICE WITH AIR GAP simplified abstract|18232937]])=== | + | ===METHOD FOR PREPARING SEMICONDUCTOR DEVICE WITH AIR GAP ([[US Patent Application 18232937. METHOD FOR PREPARING SEMICONDUCTOR DEVICE WITH AIR GAP simplified abstract (NANYA TECHNOLOGY CORPORATION)|18232937]])=== |
Line 81: | Line 57: | ||
− | ===MANUFACTURING METHOD OF SEMICONDUCTOR STRUCTURE HAVING ELASTIC MEMBER WITHIN VIA ([[US Patent Application 17752642. MANUFACTURING METHOD OF SEMICONDUCTOR STRUCTURE HAVING ELASTIC MEMBER WITHIN VIA simplified abstract|17752642]])=== | + | ===MANUFACTURING METHOD OF SEMICONDUCTOR STRUCTURE HAVING ELASTIC MEMBER WITHIN VIA ([[US Patent Application 17752642. MANUFACTURING METHOD OF SEMICONDUCTOR STRUCTURE HAVING ELASTIC MEMBER WITHIN VIA simplified abstract (NANYA TECHNOLOGY CORPORATION)|17752642]])=== |
Line 89: | Line 65: | ||
− | ===SEMICONDUCTOR STRUCTURE HAVING ELASTIC MEMBER WITHIN VIA ([[US Patent Application 17751941. SEMICONDUCTOR STRUCTURE HAVING ELASTIC MEMBER WITHIN VIA simplified abstract|17751941]])=== | + | ===SEMICONDUCTOR STRUCTURE HAVING ELASTIC MEMBER WITHIN VIA ([[US Patent Application 17751941. SEMICONDUCTOR STRUCTURE HAVING ELASTIC MEMBER WITHIN VIA simplified abstract (NANYA TECHNOLOGY CORPORATION)|17751941]])=== |
Line 97: | Line 73: | ||
− | ===METHOD OF MANUFACTURING INTEGRATED CIRCUIT DEVICE WITH BONDING STRUCTURE ([[US Patent Application 18231254. METHOD OF MANUFACTURING INTEGRATED CIRCUIT DEVICE WITH BONDING STRUCTURE simplified abstract|18231254]])=== | + | ===METHOD OF MANUFACTURING INTEGRATED CIRCUIT DEVICE WITH BONDING STRUCTURE ([[US Patent Application 18231254. METHOD OF MANUFACTURING INTEGRATED CIRCUIT DEVICE WITH BONDING STRUCTURE simplified abstract (NANYA TECHNOLOGY CORPORATION)|18231254]])=== |
Line 105: | Line 81: | ||
− | ===SEMICONDUCTOR DEVICE WITH CONTACT STRUCTURE ([[US Patent Application 17824012. SEMICONDUCTOR DEVICE WITH CONTACT STRUCTURE simplified abstract|17824012]])=== | + | ===SEMICONDUCTOR DEVICE WITH CONTACT STRUCTURE ([[US Patent Application 17824012. SEMICONDUCTOR DEVICE WITH CONTACT STRUCTURE simplified abstract (NANYA TECHNOLOGY CORPORATION)|17824012]])=== |
Line 113: | Line 89: | ||
− | ===STORAGE CAPACITOR WITH MULTIPLE DIELECTRICS ([[US Patent Application 17751936. STORAGE CAPACITOR WITH MULTIPLE DIELECTRICS simplified abstract|17751936]])=== | + | ===STORAGE CAPACITOR WITH MULTIPLE DIELECTRICS ([[US Patent Application 17751936. STORAGE CAPACITOR WITH MULTIPLE DIELECTRICS simplified abstract (NANYA TECHNOLOGY CORPORATION)|17751936]])=== |
Line 121: | Line 97: | ||
− | ===METHOD OF FABRICATING STORAGE CAPACITOR WITH MULTIPLE DIELECTRICS ([[US Patent Application 17752638. METHOD OF FABRICATING STORAGE CAPACITOR WITH MULTIPLE DIELECTRICS simplified abstract|17752638]])=== | + | ===METHOD OF FABRICATING STORAGE CAPACITOR WITH MULTIPLE DIELECTRICS ([[US Patent Application 17752638. METHOD OF FABRICATING STORAGE CAPACITOR WITH MULTIPLE DIELECTRICS simplified abstract (NANYA TECHNOLOGY CORPORATION)|17752638]])=== |
Line 129: | Line 105: | ||
− | ===METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE HAVING PROTRUSION OF WORD LINE ([[US Patent Application 17824487. METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE HAVING PROTRUSION OF WORD LINE simplified abstract|17824487]])=== | + | ===METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE HAVING PROTRUSION OF WORD LINE ([[US Patent Application 17824487. METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE HAVING PROTRUSION OF WORD LINE simplified abstract (NANYA TECHNOLOGY CORPORATION)|17824487]])=== |
Line 137: | Line 113: | ||
− | ===METHOD OF FABRICATING SEMICONDUCTOR DEVICE WITH PROGRAMMBLE FEATURE ([[US Patent Application 17825480. METHOD OF FABRICATING SEMICONDUCTOR DEVICE WITH PROGRAMMBLE FEATURE simplified abstract|17825480]])=== | + | ===METHOD OF FABRICATING SEMICONDUCTOR DEVICE WITH PROGRAMMBLE FEATURE ([[US Patent Application 17825480. METHOD OF FABRICATING SEMICONDUCTOR DEVICE WITH PROGRAMMBLE FEATURE simplified abstract (NANYA TECHNOLOGY CORPORATION)|17825480]])=== |
Line 145: | Line 121: | ||
− | ===METHOD FOR PREPARING MEMORY DEVICE HAVING PROTRUSION OF WORD LINE ([[US Patent Application 17824507. METHOD FOR PREPARING MEMORY DEVICE HAVING PROTRUSION OF WORD LINE simplified abstract|17824507]])=== | + | ===METHOD FOR PREPARING MEMORY DEVICE HAVING PROTRUSION OF WORD LINE ([[US Patent Application 17824507. METHOD FOR PREPARING MEMORY DEVICE HAVING PROTRUSION OF WORD LINE simplified abstract (NANYA TECHNOLOGY CORPORATION)|17824507]])=== |
Line 153: | Line 129: | ||
− | ===SEMICONDUCTOR DEVICE AND SEMICONDUCTOR CHIP WITH PROGRAMMABLE FEATURE ([[US Patent Application 17825057. SEMICONDUCTOR DEVICE AND SEMICONDUCTOR CHIP WITH PROGRAMMABLE FEATURE simplified abstract|17825057]])=== | + | ===SEMICONDUCTOR DEVICE AND SEMICONDUCTOR CHIP WITH PROGRAMMABLE FEATURE ([[US Patent Application 17825057. SEMICONDUCTOR DEVICE AND SEMICONDUCTOR CHIP WITH PROGRAMMABLE FEATURE simplified abstract (NANYA TECHNOLOGY CORPORATION)|17825057]])=== |
Line 161: | Line 137: | ||
− | ===SEMICONDUCTOR DEVICE HAVING PROTRUSION OF WORD LINE ([[US Patent Application 17824010. SEMICONDUCTOR DEVICE HAVING PROTRUSION OF WORD LINE simplified abstract|17824010]])=== | + | ===SEMICONDUCTOR DEVICE HAVING PROTRUSION OF WORD LINE ([[US Patent Application 17824010. SEMICONDUCTOR DEVICE HAVING PROTRUSION OF WORD LINE simplified abstract (NANYA TECHNOLOGY CORPORATION)|17824010]])=== |
Line 169: | Line 145: | ||
− | ===MEMORY STRUCTURE AND METHOD OF MANUFACTURING THE SAME ([[US Patent Application 17804095. MEMORY STRUCTURE AND METHOD OF MANUFACTURING THE SAME simplified abstract|17804095]])=== | + | ===MEMORY STRUCTURE AND METHOD OF MANUFACTURING THE SAME ([[US Patent Application 17804095. MEMORY STRUCTURE AND METHOD OF MANUFACTURING THE SAME simplified abstract (NANYA TECHNOLOGY CORPORATION)|17804095]])=== |
Line 177: | Line 153: | ||
− | ===METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE WITH PROGRAMMABLE FEATURE ([[US Patent Application 17825252. METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE WITH PROGRAMMABLE FEATURE simplified abstract|17825252]])=== | + | ===METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE WITH PROGRAMMABLE FEATURE ([[US Patent Application 17825252. METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE WITH PROGRAMMABLE FEATURE simplified abstract (NANYA TECHNOLOGY CORPORATION)|17825252]])=== |
Line 185: | Line 161: | ||
− | ===SEMICONDUCTOR DEVICE WITH PROGRAMABLE FEATURE ([[US Patent Application 17825058. SEMICONDUCTOR DEVICE WITH PROGRAMABLE FEATURE simplified abstract|17825058]])=== | + | ===SEMICONDUCTOR DEVICE WITH PROGRAMABLE FEATURE ([[US Patent Application 17825058. SEMICONDUCTOR DEVICE WITH PROGRAMABLE FEATURE simplified abstract (NANYA TECHNOLOGY CORPORATION)|17825058]])=== |
Revision as of 07:05, 5 December 2023
Contents
- 1 Patent applications for NANYA TECHNOLOGY CORPORATION on November 30th, 2023
- 1.1 VOLTAGE REGULATOR FOR PROVIDING WORD LINE VOLTAGE (17829350)
- 1.2 MEMORY DEVICE HAVING PROTRUSION OF WORD LINE (17824011)
- 1.3 SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR PREPARING THE SAME (18231912)
- 1.4 METHOD OF PREPARING ACTIVE AREAS (17828802)
- 1.5 METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH CONTACT STRUCTURE (17824481)
- 1.6 METHOD FOR PREPARING SEMICONDUCTOR DEVICE WITH AIR SPACER (18232833)
- 1.7 METHOD FOR PREPARING SEMICONDUCTOR DEVICE WITH AIR GAP (18232937)
- 1.8 MANUFACTURING METHOD OF SEMICONDUCTOR STRUCTURE HAVING ELASTIC MEMBER WITHIN VIA (17752642)
- 1.9 SEMICONDUCTOR STRUCTURE HAVING ELASTIC MEMBER WITHIN VIA (17751941)
- 1.10 METHOD OF MANUFACTURING INTEGRATED CIRCUIT DEVICE WITH BONDING STRUCTURE (18231254)
- 1.11 SEMICONDUCTOR DEVICE WITH CONTACT STRUCTURE (17824012)
- 1.12 STORAGE CAPACITOR WITH MULTIPLE DIELECTRICS (17751936)
- 1.13 METHOD OF FABRICATING STORAGE CAPACITOR WITH MULTIPLE DIELECTRICS (17752638)
- 1.14 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE HAVING PROTRUSION OF WORD LINE (17824487)
- 1.15 METHOD OF FABRICATING SEMICONDUCTOR DEVICE WITH PROGRAMMBLE FEATURE (17825480)
- 1.16 METHOD FOR PREPARING MEMORY DEVICE HAVING PROTRUSION OF WORD LINE (17824507)
- 1.17 SEMICONDUCTOR DEVICE AND SEMICONDUCTOR CHIP WITH PROGRAMMABLE FEATURE (17825057)
- 1.18 SEMICONDUCTOR DEVICE HAVING PROTRUSION OF WORD LINE (17824010)
- 1.19 MEMORY STRUCTURE AND METHOD OF MANUFACTURING THE SAME (17804095)
- 1.20 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE WITH PROGRAMMABLE FEATURE (17825252)
- 1.21 SEMICONDUCTOR DEVICE WITH PROGRAMABLE FEATURE (17825058)
Patent applications for NANYA TECHNOLOGY CORPORATION on November 30th, 2023
VOLTAGE REGULATOR FOR PROVIDING WORD LINE VOLTAGE (17829350)
Main Inventor
Chih-Jen Chen
MEMORY DEVICE HAVING PROTRUSION OF WORD LINE (17824011)
Main Inventor
JAR-MING HO
SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR PREPARING THE SAME (18231912)
Main Inventor
CHENG-HSIANG FAN
METHOD OF PREPARING ACTIVE AREAS (17828802)
Main Inventor
YING-CHENG CHUANG
METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH CONTACT STRUCTURE (17824481)
Main Inventor
CHIH-HSUAN YEH
METHOD FOR PREPARING SEMICONDUCTOR DEVICE WITH AIR SPACER (18232833)
Main Inventor
JUNG-HSING CHIEN
METHOD FOR PREPARING SEMICONDUCTOR DEVICE WITH AIR GAP (18232937)
Main Inventor
LIANG-PIN CHOU
MANUFACTURING METHOD OF SEMICONDUCTOR STRUCTURE HAVING ELASTIC MEMBER WITHIN VIA (17752642)
Main Inventor
SHING-YIH SHIH
SEMICONDUCTOR STRUCTURE HAVING ELASTIC MEMBER WITHIN VIA (17751941)
Main Inventor
SHING-YIH SHIH
METHOD OF MANUFACTURING INTEGRATED CIRCUIT DEVICE WITH BONDING STRUCTURE (18231254)
Main Inventor
TZU-CHING TSAI
SEMICONDUCTOR DEVICE WITH CONTACT STRUCTURE (17824012)
Main Inventor
CHIH-HSUAN YEH
STORAGE CAPACITOR WITH MULTIPLE DIELECTRICS (17751936)
Main Inventor
KAI-HUNG LIN
METHOD OF FABRICATING STORAGE CAPACITOR WITH MULTIPLE DIELECTRICS (17752638)
Main Inventor
KAI-HUNG LIN
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE HAVING PROTRUSION OF WORD LINE (17824487)
Main Inventor
CHIN-TE KUO
METHOD OF FABRICATING SEMICONDUCTOR DEVICE WITH PROGRAMMBLE FEATURE (17825480)
Main Inventor
YIN-FA CHEN
METHOD FOR PREPARING MEMORY DEVICE HAVING PROTRUSION OF WORD LINE (17824507)
Main Inventor
JAR-MING HO
SEMICONDUCTOR DEVICE AND SEMICONDUCTOR CHIP WITH PROGRAMMABLE FEATURE (17825057)
Main Inventor
YIN-FA CHEN
SEMICONDUCTOR DEVICE HAVING PROTRUSION OF WORD LINE (17824010)
Main Inventor
CHIN-TE KUO
MEMORY STRUCTURE AND METHOD OF MANUFACTURING THE SAME (17804095)
Main Inventor
Wei-Chih WANG
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE WITH PROGRAMMABLE FEATURE (17825252)
Main Inventor
YIN-FA CHEN
SEMICONDUCTOR DEVICE WITH PROGRAMABLE FEATURE (17825058)
Main Inventor
YIN-FA CHEN