View source for US Patent Application 18447372. Semiconductor Device Including a Level Shifter and Method of Mitigating a Delay Between Input and Output Signals simplified abstract

=Semiconductor Device Including a Level Shifter and Method of Mitigating a Delay Between Input and Output Signals=


==Organization Name==

[[:Category:Taiwan Semiconductor Manufacturing Company, Ltd.|Taiwan Semiconductor Manufacturing Company, Ltd.]]


[[Category:Taiwan Semiconductor Manufacturing Company, Ltd.]]==Inventor(s)==

[[Category:[[:Category:Jerrin Pathrose Vareed of Hsinchu (TW)|Jerrin Pathrose Vareed of Hsinchu (TW)]]]]

[[Category:[[:Category:Shiba Mohanty of Hsinchu (TW)|Shiba Mohanty of Hsinchu (TW)]]]]

==Semiconductor Device Including a Level Shifter and Method of Mitigating a Delay Between Input and Output Signals - A simplified explanation of the abstract==


This abstract first appeared for US patent application 18447372 titled 'Semiconductor Device Including a Level Shifter and Method of Mitigating a Delay Between Input and Output Signals

==Simplified Explanation==

The patent application describes a semiconductor device that includes an input, a level shifter, an output, and a switch module. 

* The input receives an input signal in a first voltage domain.
* The level shifter is connected to the input and shifts the input signal from the first voltage domain to a second voltage domain.
* The switch module connects either the input or the level shifter to the output.
* The purpose of the invention is to mitigate the delay between input and output signals of the semiconductor device.


==Original Abstract Submitted==

A semiconductor device includes an input, a level shifter, an output, and a switch module. The input is configured to receive an input signal in a first voltage domain. The level shifter is connected to the input and is configured to shift the input signal from the first voltage domain to a second voltage domain. The switch module is configured to connect one of the input and the level shifter to the output. A method of mitigating a delay between input and output signals of the semiconductor device is also disclosed.



[[Category:H03K19/0185]]
[[Category:H03K3/037]]