View source for US Patent Application 18446546. STATIC RANDOM ACCESS MEMORY WITH PRE-CHARGE CIRCUIT simplified abstract

=STATIC RANDOM ACCESS MEMORY WITH PRE-CHARGE CIRCUIT=


==Organization Name==

[[:Category:Taiwan Semiconductor Manufacturing Company, Ltd.|Taiwan Semiconductor Manufacturing Company, Ltd.]]


[[Category:Taiwan Semiconductor Manufacturing Company, Ltd.]]

==Inventor(s)==

[[:Category:Po-Sheng Wang of Hsinchu (TW)|Po-Sheng Wang of Hsinchu (TW)]][[Category:Po-Sheng Wang of Hsinchu (TW)]]

[[:Category:Yangsyu Lin of New Taipei City (TW)|Yangsyu Lin of New Taipei City (TW)]][[Category:Yangsyu Lin of New Taipei City (TW)]]

[[:Category:Cheng Hung Lee of Hsinchu (TW)|Cheng Hung Lee of Hsinchu (TW)]][[Category:Cheng Hung Lee of Hsinchu (TW)]]

==STATIC RANDOM ACCESS MEMORY WITH PRE-CHARGE CIRCUIT - A simplified explanation of the abstract==


This abstract first appeared for US patent application 18446546 titled 'STATIC RANDOM ACCESS MEMORY WITH PRE-CHARGE CIRCUIT

==Simplified Explanation==

The patent application describes a memory device with a pre-charge circuit.
* The memory device includes a memory cell and a pre-charge circuit.
* The pre-charge circuit consists of two transistors - a first transistor and a second transistor.
* The first transistor has a first gate terminal, a first source/drain terminal connected to a reference voltage, and a second source/drain terminal connected to one terminal of the memory cell.
* The second transistor has a second gate terminal, a third source/drain terminal connected to the reference voltage, and a fourth source/drain terminal connected to the other terminal of the memory cell.
* The first and second transistors are designed to allow the reference voltage to pass through when a control signal is applied to their respective gate terminals.


==Original Abstract Submitted==

The present disclosure describes embodiments of a memory device with a pre-charge circuit. The memory device can include a memory cell, and the pre-charge circuit can include a first transistor and a second transistor. The first transistor includes a first gate terminal, a first source/drain (S/D) terminal coupled to a reference voltage, and a second S/D terminal coupled to a first terminal of the memory cell. The second transistor includes a second gate terminal, a third S/D terminal coupled to the reference voltage, and a fourth S/D terminal coupled to the second terminal of the memory cell. The first and second transistors are configured to pass the reference voltage in response to the control signal being applied to the first and second gate terminals, respectively.



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[[Category:G11C11/419]]
[[Category:G11C11/412]]