View source for US Patent Application 18364679. INTEGRATION OF P-CHANNEL AND N-CHANNEL E-FET III-V DEVICES WITH OPTIMIZATION OF DEVICE PERFORMANCE simplified abstract

=INTEGRATION OF P-CHANNEL AND N-CHANNEL E-FET III-V DEVICES WITH OPTIMIZATION OF DEVICE PERFORMANCE=


==Organization Name==

[[:Category:Taiwan Semiconductor Manufacturing Company, Ltd.|Taiwan Semiconductor Manufacturing Company, Ltd.]]


[[Category:Taiwan Semiconductor Manufacturing Company, Ltd.]]==Inventor(s)==

[[Category:[[:Category:Man-Ho Kwan of Hsin-Chu (TW)|Man-Ho Kwan of Hsin-Chu (TW)]]]]

[[Category:[[:Category:Fu-Wei Yao of Hsinchu City (TW)|Fu-Wei Yao of Hsinchu City (TW)]]]]

[[Category:[[:Category:Chun Lin Tsai of Hsin-Chu (TW)|Chun Lin Tsai of Hsin-Chu (TW)]]]]

[[Category:[[:Category:Jiun-Lei Jerry Yu of Zhudong Township (TW)|Jiun-Lei Jerry Yu of Zhudong Township (TW)]]]]

[[Category:[[:Category:Ting-Fu Chang of Hsinchu City (TW)|Ting-Fu Chang of Hsinchu City (TW)]]]]

==INTEGRATION OF P-CHANNEL AND N-CHANNEL E-FET III-V DEVICES WITH OPTIMIZATION OF DEVICE PERFORMANCE - A simplified explanation of the abstract==


This abstract first appeared for US patent application 18364679 titled 'INTEGRATION OF P-CHANNEL AND N-CHANNEL E-FET III-V DEVICES WITH OPTIMIZATION OF DEVICE PERFORMANCE

==Simplified Explanation==

The patent application describes an integrated chip design with specific layers and regions for n-channel and p-channel devices.

* The chip has a substrate, with a first undoped layer on top.
* A first barrier layer is on top of the first undoped layer, with a specific thickness.
* A first doped layer is on top of the first barrier layer, specifically within the n-channel device region.
* A second barrier layer is on top of the first barrier layer, specifically within the p-channel device region.
* The second barrier layer has a greater thickness than the first barrier layer.
* A second undoped layer is on top of the second barrier layer.
* A second doped layer is on top of the second undoped layer.
* The second undoped layer and second doped layer are specifically within the p-channel device region.


==Original Abstract Submitted==

Various embodiments of the present disclosure are directed towards an integrated chip a first undoped layer overlies a substrate. A first barrier layer overlies the first undoped layer and has a first thickness. A first doped layer overlies the first barrier layer and is disposed laterally within an n-channel device region of the substrate. A second barrier layer overlies the first barrier layer and is disposed within a p-channel device region that is laterally adjacent to the n-channel device region. The second barrier layer has a second thickness that is greater than the first thickness. A second undoped layer overlies the second barrier layer. A second doped layer overlies the second undoped layer. The second undoped layer and the second doped layer are disposed within the p-channel device region.



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