View source for US Patent Application 18345411. VECTOR-BASED PACKET PROCESSING METHOD AND APPARATUS IN USER PLANE FUNCTION simplified abstract

=VECTOR-BASED PACKET PROCESSING METHOD AND APPARATUS IN USER PLANE FUNCTION=


==Organization Name==

[[Samsung Electronics Co., Ltd.]]


==Inventor(s)==

[[Jihwan Seo of Suwon-si (KR)]]


[[Seonjun Park of Suwon-si (KR)]]


[[Beomseok Oh of Suwon-si (KR)]]


[[Sewon Oh of Suwon-si (KR)]]


==VECTOR-BASED PACKET PROCESSING METHOD AND APPARATUS IN USER PLANE FUNCTION - A simplified explanation of the abstract==


This abstract first appeared for US patent application 18345411 titled 'VECTOR-BASED PACKET PROCESSING METHOD AND APPARATUS IN USER PLANE FUNCTION

==Simplified Explanation==

The abstract describes a user plane function (UPF) packet processing control apparatus.
* The apparatus includes a processor and a memory storing instructions.
* The processor executes the instructions to analyze the state of UPF packet processing by multiple packet processing pipelines.
* Based on the analysis, the apparatus determines the size of a packet vector for each packet processing pipeline.
* The apparatus also allocates a number of processing cores to each packet processing pipeline based on the analysis.

Bullet points explaining the patent/innovation:
* The patent application describes a technology for controlling the processing of UPF packets in a network.
* The apparatus analyzes the current state of packet processing pipelines to optimize their performance.
* By determining the size of a packet vector for each pipeline, the apparatus can efficiently handle packets.
* The allocation of processing cores to each pipeline is based on the analysis, ensuring optimal resource utilization.
* This technology aims to improve the overall efficiency and performance of UPF packet processing in a network.


==Original Abstract Submitted==

Disclosed is a user plane function (UPF) packet processing control apparatus including: a processor, and a memory storing instructions, wherein the processor is configured to execute the instructions to analyze a state in which UPF packets are processed by a plurality of packet processing pipelines, determine a size of a packet vector for each of the plurality of packet processing pipelines based on a result of the analyzing, and allocate a number of processing cores to each of the plurality of packet processing pipelines based on the result of the analyzing.