View source for US Patent Application 18300162. Vertically Integrated Device Stack Including System on Chip and Power Management Integrated Circuit simplified abstract

=Vertically Integrated Device Stack Including System on Chip and Power Management Integrated Circuit=


==Organization Name==

[[:Category:QUALCOMM Incorporated|QUALCOMM Incorporated]]


[[Category:QUALCOMM Incorporated]]==Inventor(s)==

[[Category:[[:Category:Peng Zou of Camas WA (US)|Peng Zou of Camas WA (US)]]]]

[[Category:[[:Category:Syrus Ziai of Los Altos CA (US)|Syrus Ziai of Los Altos CA (US)]]]]

==Vertically Integrated Device Stack Including System on Chip and Power Management Integrated Circuit - A simplified explanation of the abstract==


This abstract first appeared for US patent application 18300162 titled 'Vertically Integrated Device Stack Including System on Chip and Power Management Integrated Circuit

==Simplified Explanation==

The patent application describes a semiconductor device that consists of a package substrate, a system-on-chip (SoC) die, and a power management integrated circuit (PMIC) die arranged in a vertical stack.
* The SoC die is placed on the top surface of the package substrate, while the PMIC die is mechanically connected to the bottom surface of the package substrate.
* The PMIC die is electrically connected to the SoC die through via connectors on the package substrate, allowing it to provide DC power to the SoC die.
* The PMIC die includes thin film inductors on its surface, which are located next to the bottom surface of the package substrate.
* The purpose of this innovation is to improve the power management capabilities of the semiconductor device by efficiently transferring DC power from the PMIC die to the SoC die.


==Original Abstract Submitted==

A semiconductor device has a package substrate, a system-on-chip (SoC) die, and a power management integrated circuit (PMIC) die, arranged in a vertical stack. The SoC die is disposed on a first surface of the package substrate, and the PMIC die is mechanically coupled to a second surface of the package substrate. The PMIC die is electrically coupled to the SOC die via first via connectors of the package substrate and configured to provide DC power to the SOC die via DC connectors electrically coupled to the via connectors of the package substrate. The PMIC die includes thin film inductors, corresponding to the DC connectors, on a surface of the PMIC die and located adjacent to the second surface of the package substrate.



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