View source for US Patent Application 18298305. System and Method for Receiver Equalization and Stressed Eye Testing Methodology for DDR5 Memory Controller simplified abstract

=System and Method for Receiver Equalization and Stressed Eye Testing Methodology for DDR5 Memory Controller=


==Inventors==

[[Gang Zhao of Chandler AZ (US)]]


[[Howard David of Portland OR (US)]]


[[Xusheng Liu of Shenzhen (CN)]]


[[Yongyao Li of Chengdu (CN)]]


==System and Method for Receiver Equalization and Stressed Eye Testing Methodology for DDR5 Memory Controller - A simplified explanation of the abstract==


*This abstract for appeared for patent application  number 18298305 Titled 'System and Method for Receiver Equalization and Stressed Eye Testing Methodology for DDR5 Memory Controller'

==Simplified Explanation==

The abstract describes a method for testing the bit error rate of a processing unit using a bit error rate tester (BERT). The method involves transmitting a signal pair to the receiver of the processing unit, with the signal pair having jitter levels that meet a specified threshold. The signal pair is then adjusted to obtain a stressed eye measurement for the receiver that meets a stressed eye mask. The processing unit is then placed into a loop-back mode, where data transmitted by the BERT is sent back to the BERT. A data pattern is transmitted to the processing unit and a looped back version of the data pattern is received. The bit error rate is then calculated based on the data pattern and the looped back version of the data pattern.


==Original Abstract Submitted==

A method for bit error rate testing a processing unit using a bit error rate tester (BERT) includes transmitting a signal pair to a receiver of the processing unit, the signal pair having jitter levels complying with a jitter threshold, tuning the signal pair to obtain a first stressed eye measurement for the receiver, wherein the first stressed eye measurement complies with a stressed eye mask, placing the processing unit into a loop-back mode, wherein data transmitted to the processing unit by the BERT is transmitted back to the BERT, transmitting a data pattern to the processing unit, receiving a looped back version of the data pattern from the processing unit, and calculating a bit error rate in accordance with the data pattern and the looped back version of the data pattern.