View source for Taiwan semiconductor manufacturing company, ltd. (20250151359). SEMICONDUCTOR DEVICE STRUCTURE

<!-- JSON-LD markup for search engines:
{"@context":"https://schema.org","@type":"TechArticle","headline":"SEMICONDUCTOR DEVICE STRUCTURE","name":"SEMICONDUCTOR DEVICE STRUCTURE","description":"a semiconductor device structure is provided. the semiconductor device structure includes a plurality of first nanostructures stacked over a substrate in a vertical direction. the semiconductor device...","datePublished":"May 8th, 2025","mainEntity":{"@type":"Patent","identifier":"20250151359","name":"SEMICONDUCTOR DEVICE STRUCTURE","abstract":"a semiconductor device structure is provided. the semiconductor device structure includes a plurality of first nanostructures stacked over a substrate in a vertical direction. the semiconductor device structure includes a first gate structure surrounding the first nanostructures. the semiconductor device structure also includes a first gate spacer layer formed adjacent to the first gate structure. a topmost first nanostructure has a first portion below the gate spacer layer and a second portion below the first gate structure, and the first portion has a first height along the vertical direction, the second portion has a second height along the vertical direction, and the first height is greater than the second height.","applicationNumber":"20250151359","datePublished":"May 8th, 2025","inventor":[{"@type":"Person","name":"Yi-Ruei JHAN"},{"@type":"Person","name":"Kuo-Cheng CHIANG"},{"@type":"Person","name":"Chih-Hao WANG"}],"applicant":{"@type":"Organization","name":"taiwan semiconductor manufacturing company, ltd."},"additionalProperty":[{"@type":"PropertyValue","name":"IPC Classification","value":"H10D64/01"},{"@type":"PropertyValue","name":"IPC Classification","value":"H10D30/01"},{"@type":"PropertyValue","name":"IPC Classification","value":"H10D30/67"},{"@type":"PropertyValue","name":"IPC Classification","value":"H10D62/10"},{"@type":"PropertyValue","name":"IPC Classification","value":"H10D62/13"},{"@type":"PropertyValue","name":"IPC Classification","value":"H10D64/23"},{"@type":"PropertyValue","name":"IPC Classification","value":"H10D84/83"},{"@type":"PropertyValue","name":"CPC Classification","value":"H10D64/017"}]}}
-->

=SEMICONDUCTOR DEVICE STRUCTURE=


==Organization Name==

[[:Category:taiwan semiconductor manufacturing company, ltd.|taiwan semiconductor manufacturing company, ltd.]]


[[Category:taiwan semiconductor manufacturing company, ltd.]]

==Inventor(s)==

[[:Category:Yi-Ruei Jhan of Keelung City TW|Yi-Ruei Jhan of Keelung City TW]][[Category:Yi-Ruei Jhan of Keelung City TW]]

[[:Category:Kuo-Cheng Chiang of Zhubei City TW|Kuo-Cheng Chiang of Zhubei City TW]][[Category:Kuo-Cheng Chiang of Zhubei City TW]]

[[:Category:Chih-Hao Wang of Baoshan Township TW|Chih-Hao Wang of Baoshan Township TW]][[Category:Chih-Hao Wang of Baoshan Township TW]]

==SEMICONDUCTOR DEVICE STRUCTURE==


This abstract first appeared for US patent application 20250151359 titled 'SEMICONDUCTOR DEVICE STRUCTURE

==Original Abstract Submitted==

a semiconductor device structure is provided. the semiconductor device structure includes a plurality of first nanostructures stacked over a substrate in a vertical direction. the semiconductor device structure includes a first gate structure surrounding the first nanostructures. the semiconductor device structure also includes a first gate spacer layer formed adjacent to the first gate structure. a topmost first nanostructure has a first portion below the gate spacer layer and a second portion below the first gate structure, and the first portion has a first height along the vertical direction, the second portion has a second height along the vertical direction, and the first height is greater than the second height.



[[Category:H10D64/01]]
[[Category:H10D30/01]]
[[Category:H10D30/67]]
[[Category:H10D62/10]]
[[Category:H10D62/13]]
[[Category:H10D64/23]]
[[Category:H10D84/83]]
[[Category:CPC_H10D64/017]]