View source for Sony semiconductor solutions corporation (20250006260). SEMICONDUCTOR STORAGE DEVICE

=SEMICONDUCTOR STORAGE DEVICE=


==Organization Name==

[[:Category:sony semiconductor solutions corporation|sony semiconductor solutions corporation]]


[[Category:sony semiconductor solutions corporation]]

==Inventor(s)==

[[:Category:ISAO Naritake of KANAGAWA (JP)|ISAO Naritake of KANAGAWA (JP)]][[Category:ISAO Naritake of KANAGAWA (JP)]]

[[:Category:NOBUYUKI Ishikawa of KANAGAWA (JP)|NOBUYUKI Ishikawa of KANAGAWA (JP)]][[Category:NOBUYUKI Ishikawa of KANAGAWA (JP)]]

[[:Category:YOSHIHIKO Kinoshita of KANAGAWA (JP)|YOSHIHIKO Kinoshita of KANAGAWA (JP)]][[Category:YOSHIHIKO Kinoshita of KANAGAWA (JP)]]

[[:Category:TETSUO Motomura of KANAGAWA (JP)|TETSUO Motomura of KANAGAWA (JP)]][[Category:TETSUO Motomura of KANAGAWA (JP)]]

[[:Category:KAZUFUMI Ikeda of KANAGAWA (JP)|KAZUFUMI Ikeda of KANAGAWA (JP)]][[Category:KAZUFUMI Ikeda of KANAGAWA (JP)]]

[[:Category:TSUKASA Ojiro of KANAGAWA (JP)|TSUKASA Ojiro of KANAGAWA (JP)]][[Category:TSUKASA Ojiro of KANAGAWA (JP)]]

[[:Category:TOMOKO Shimada of KANAGAWA (JP)|TOMOKO Shimada of KANAGAWA (JP)]][[Category:TOMOKO Shimada of KANAGAWA (JP)]]

[[:Category:KENICHI Nagamatsu of KANAGAWA (JP)|KENICHI Nagamatsu of KANAGAWA (JP)]][[Category:KENICHI Nagamatsu of KANAGAWA (JP)]]

[[:Category:KOJI Watanabe of KANAGAWA (JP)|KOJI Watanabe of KANAGAWA (JP)]][[Category:KOJI Watanabe of KANAGAWA (JP)]]

==SEMICONDUCTOR STORAGE DEVICE==


This abstract first appeared for US patent application 20250006260 titled 'SEMICONDUCTOR STORAGE DEVICE




==Original Abstract Submitted==

[solution] a semiconductor storage device includes: one or more first memory cells connected in parallel between a first voltage supply line supplying a first voltage and a second voltage supply line supplying a second voltage different from the first voltage; and one or more second memory cells connected in parallel between the second voltage supply line and a third voltage supply line supplying the first voltage, wherein each of the first memory cells includes: a first storage element having a resistance value corresponding to a first status or a second status; and a first cell transistor connected between the first storage element and the first voltage supply line, and each of the second memory cells includes: a second storage element having a resistance value corresponding to a first status or a second status; and a second cell transistor connected between the second storage element and the third voltage supply line.



[[Category:G11C13/00]]
[[Category:CPC_G11C13/004]]