View source for Nvidia corporation (20240353475). INTEGRATED CURRENT MONITOR simplified abstract

=INTEGRATED CURRENT MONITOR=


==Organization Name==

[[:Category:nvidia corporation|nvidia corporation]]


[[Category:nvidia corporation]]

==Inventor(s)==

[[:Category:Miguel Rodriguez of Santa Clara CA (US)|Miguel Rodriguez of Santa Clara CA (US)]][[Category:Miguel Rodriguez of Santa Clara CA (US)]]

[[:Category:Suhas Satheesh of Santa Clara CA (US)|Suhas Satheesh of Santa Clara CA (US)]][[Category:Suhas Satheesh of Santa Clara CA (US)]]

[[:Category:Tezaswi Raja of Santa Clara CA (US)|Tezaswi Raja of Santa Clara CA (US)]][[Category:Tezaswi Raja of Santa Clara CA (US)]]

[[:Category:Nishit Harshad Shah of Santa Clara CA (US)|Nishit Harshad Shah of Santa Clara CA (US)]][[Category:Nishit Harshad Shah of Santa Clara CA (US)]]

==INTEGRATED CURRENT MONITOR - A simplified explanation of the abstract==


This abstract first appeared for US patent application 20240353475 titled 'INTEGRATED CURRENT MONITOR

'''Simplified Explanation:'''
The patent application describes a method for determining electrical characteristics of material in a specific area of a semiconductor wafer by sourcing or sinking current through selected devices, converting the current into voltage, comparing it against a linear voltage ramp, generating an output clock, and measuring the duty cycle of the clock.

* The method involves sourcing or sinking current through devices on a semiconductor wafer.
* The current is converted into voltage and compared against a linear voltage ramp.
* An output clock is generated based on the comparison.
* The duty cycle of the output clock is measured to determine electrical characteristics of the material in the specific area of the wafer.

'''Key Features and Innovation:'''
* Method for determining electrical characteristics of material in a specific area of a semiconductor wafer.
* Utilizes current sourcing or sinking, voltage conversion, comparison against a linear voltage ramp, and duty cycle measurement.
* Provides a way to analyze the material properties in a localized manner on the wafer.

'''Potential Applications:'''
* Semiconductor manufacturing industry for quality control and process optimization.
* Research and development in semiconductor materials and devices.
* Testing and characterization of new semiconductor materials.

'''Problems Solved:'''
* Enables precise determination of electrical characteristics in specific areas of a semiconductor wafer.
* Provides a localized analysis method for material properties.
* Improves efficiency and accuracy in semiconductor testing processes.

'''Benefits:'''
* Enhanced understanding of material properties in semiconductor wafers.
* Enables targeted analysis for quality control and optimization.
* Facilitates innovation in semiconductor manufacturing processes.

'''Commercial Applications:'''
Potential commercial applications of this technology could include:
* Quality control in semiconductor manufacturing.
* Research and development in semiconductor materials.
* Testing services for semiconductor companies.

'''Questions about the Technology:'''
1. How does this method improve upon existing techniques for analyzing material properties in semiconductor wafers?
2. What are the potential implications of using this technology for semiconductor manufacturing processes?


==Original Abstract Submitted==

circuitry and a method of determining electrical characteristics of material local to a specific area of a semiconductor wafer is disclosed. in one embodiment, the method includes sinking or sourcing current through a selected on of a plurality of devices under test (duts) on the semiconductor wafer, converting the current sourcing or sinking into a voltage, comparing the converted voltage against a linear voltage ramp, generating an output clock based on the comparison, and measuring a duty cycle of the output clock. in one embodiment, the duty cycle of the output clock is dependent on the current sinking or sourcing through the selected at least one of the plurality of duts on the wafer and electrical characteristics of material local to the specific area of the wafer where the selected one of the plurality of duts is located are determined based on the duty cycle of the output clock.



[[Category:G01R31/28]]
[[Category:H03K17/687]]
[[Category:CPC_G01R31/2839]]