View source for Nvidia corporation (20240340157). LOW POWER AND AREA CLOCK MONITORING CIRCUIT USING RING DELAY ARRANGEMENT FOR CLOCK SIGNAL HAVING PHASE-TO-PHASE VARIATION simplified abstract

=LOW POWER AND AREA CLOCK MONITORING CIRCUIT USING RING DELAY ARRANGEMENT FOR CLOCK SIGNAL HAVING PHASE-TO-PHASE VARIATION=


==Organization Name==

[[:Category:nvidia corporation|nvidia corporation]]


[[Category:nvidia corporation]]

==Inventor(s)==

[[:Category:Kedar Rajpathak of Santa Clara CA (US)|Kedar Rajpathak of Santa Clara CA (US)]][[Category:Kedar Rajpathak of Santa Clara CA (US)]]

[[:Category:Tezaswi Raja of Santa Clara CA (US)|Tezaswi Raja of Santa Clara CA (US)]][[Category:Tezaswi Raja of Santa Clara CA (US)]]

==LOW POWER AND AREA CLOCK MONITORING CIRCUIT USING RING DELAY ARRANGEMENT FOR CLOCK SIGNAL HAVING PHASE-TO-PHASE VARIATION - A simplified explanation of the abstract==


This abstract first appeared for US patent application 20240340157 titled 'LOW POWER AND AREA CLOCK MONITORING CIRCUIT USING RING DELAY ARRANGEMENT FOR CLOCK SIGNAL HAVING PHASE-TO-PHASE VARIATION

'''Simplified Explanation:'''
The patent application describes a circuit and method for monitoring a clock signal with phase-to-phase variation. By adjusting pulse counts based on the reference phase instance, abnormalities in the clock signal can be detected.

* Adding a fixed number of bits to the pulse count for a reference phase instance detects a clock slow abnormality.
* Subtracting the fixed number of bits from the pulse count for the reference phase instance detects a clock fast abnormality.
* Comparing the modified pulse counts with subsequent phase instances helps identify abnormal clock behavior.

'''Key Features and Innovation:'''
* Circuitry for monitoring clock signals with phase-to-phase variation.
* Method for detecting clock abnormalities by adjusting pulse counts.
* Comparison of pulse counts for abnormality detection.

'''Potential Applications:'''
This technology can be used in various electronic devices that rely on precise timing signals, such as computers, communication systems, and industrial equipment.

'''Problems Solved:'''
The technology addresses the need for accurate monitoring of clock signals to ensure proper functioning of electronic systems.

'''Benefits:'''
* Early detection of clock abnormalities.
* Improved reliability and performance of electronic devices.
* Enhanced troubleshooting capabilities for timing issues.

'''Commercial Applications:'''
The technology can be applied in the development of high-performance computing systems, telecommunications infrastructure, and advanced manufacturing equipment, enhancing their efficiency and reliability.

'''Prior Art:'''
Researchers can explore prior patents related to clock signal monitoring, phase detection circuits, and abnormality detection in electronic systems for further insights into this technology.

'''Frequently Updated Research:'''
Stay informed about advancements in clock signal monitoring, phase detection techniques, and real-time abnormality detection in electronic circuits to leverage the latest innovations in this field.

'''Questions about Clock Signal Monitoring:'''
1. How does this technology improve the accuracy of clock signal monitoring?
2. What are the potential challenges in implementing this circuitry in different electronic systems?


==Original Abstract Submitted==

circuitry and method of operating a circuit for monitoring a clock signal having phase-to-phase variation is disclosed. the method comprises adding a fixed number of bits to a pulse count of a reference phase instance for a high or low phase to yield a modified added pulse count when detecting a clock slow abnormality, subtracting the fixed number of bits from the pulse count of the reference phase instance to yield a modified subtracted pulse count when detecting a clock fast abnormality, comparing the modified added pulse count to a pulse count for an immediately subsequent phase instance of the high or low phase count of the clock signal when detecting the clock slow abnormality, and comparing the modified subtracted pulse count to the pulse count for the immediately subsequent phase instance of the high phase or low phase count of the clock signal when detecting the clock fast abnormality.



[[Category:H04L7/033]]
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