View source for Micron technology, inc. (20240161796). Programmable Memory Timing simplified abstract

=Programmable Memory Timing=


==Organization Name==

[[:Category:micron technology, inc.|micron technology, inc.]]


[[Category:micron technology, inc.]]

==Inventor(s)==

[[:Category:Kang-Yong Kim of Boise ID (US)|Kang-Yong Kim of Boise ID (US)]][[Category:Kang-Yong Kim of Boise ID (US)]]

[[:Category:Hyun Yoo Lee of Boise ID (US)|Hyun Yoo Lee of Boise ID (US)]][[Category:Hyun Yoo Lee of Boise ID (US)]]

[[:Category:Timothy M. Hollis of Meridian ID (US)|Timothy M. Hollis of Meridian ID (US)]][[Category:Timothy M. Hollis of Meridian ID (US)]]

[[:Category:Dong Soon Lim of Boise ID (US)|Dong Soon Lim of Boise ID (US)]][[Category:Dong Soon Lim of Boise ID (US)]]

==Programmable Memory Timing - A simplified explanation of the abstract==


This abstract first appeared for US patent application 20240161796 titled 'Programmable Memory Timing

==Simplified Explanation==

The patent application describes apparatuses and methods for establishing relative delays between different data lines in order to mitigate simultaneous switching output (SSO) and crosstalk issues that can impact channel timing budget parameters. 

* The system includes an interconnect with multiple data lines connecting a host device to a memory device.
* The host device can transmit a command indicating a phase offset between data lines.
* The memory device can adjust the relative phase offsets between data lines based on the command.
* The host device can determine appropriate offsets for the system.
* The system can activate phase offsets based on frequency variations.

== Potential Applications ==
This technology can be applied in high-speed data communication systems, such as in computer memory modules and data storage devices.

== Problems Solved ==
This technology addresses issues related to simultaneous switching output (SSO) and crosstalk that can affect channel timing budget parameters in data communication systems.

== Benefits ==
The benefits of this technology include improved data transmission reliability, reduced signal interference, and enhanced overall system performance.

== Potential Commercial Applications ==
Potential commercial applications of this technology include computer memory modules, data storage devices, networking equipment, and other high-speed data communication systems.

== Possible Prior Art ==
One possible prior art related to this technology is the use of phase-locked loops (PLLs) in data communication systems to adjust signal timing and reduce interference.

=== What are the specific technical details of the command transmitted by the host device to indicate phase offsets between data lines? ===

The specific technical details of the command transmitted by the host device to indicate phase offsets between data lines involve encoding the phase offset information in a format that can be interpreted by the memory device. This could include using specific bits or bytes in the command packet to represent the desired phase offset values.

=== How does the system determine the appropriate offsets for a given apparatus? ===

The system determines the appropriate offsets for a given apparatus based on factors such as the operating frequency, signal characteristics, and system requirements. This could involve analyzing the data transmission performance under different offset configurations and selecting the offsets that optimize system performance.


==Original Abstract Submitted==

described apparatuses and methods enable communication between a host device and a memory device to establish relative delays between different data lines. if data signals propagate along a bus with the same timing, simultaneous switching output (sso) and crosstalk can adversely impact channel timing budget parameters. an example system includes an interconnect having multiple data lines that couple the host device to the memory device. in example operations, the host device can transmit to the memory device a command indicative of a phase offset between two or more data lines of the multiple data lines. the memory device can implement the command by transmitting or receiving signals via the interconnect with different relative phase offsets between data lines. the host device (e.g., a memory controller) can determine appropriate offsets for a given apparatus. lengths of the offsets can vary. further, a system can activate the phase offsets based on frequency.



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