View source for Intel corporation (20250117359). DUAL PIPELINE PARALLEL SYSTOLIC ARRAY

=DUAL PIPELINE PARALLEL SYSTOLIC ARRAY=


==Organization Name==

[[:Category:intel corporation|intel corporation]]


[[Category:intel corporation]]

==Inventor(s)==

[[:Category:Jorge Parra of El Dorado Hills CA US|Jorge Parra of El Dorado Hills CA US]][[Category:Jorge Parra of El Dorado Hills CA US]]

[[:Category:Jiasheng Chen of El Dorado Hills CA US|Jiasheng Chen of El Dorado Hills CA US]][[Category:Jiasheng Chen of El Dorado Hills CA US]]

[[:Category:Supratim Pal of Folsom CA US|Supratim Pal of Folsom CA US]][[Category:Supratim Pal of Folsom CA US]]

[[:Category:Fangwen Fu of Folsom CA US|Fangwen Fu of Folsom CA US]][[Category:Fangwen Fu of Folsom CA US]]

[[:Category:Sabareesh Ganapathy of Bangalore IN|Sabareesh Ganapathy of Bangalore IN]][[Category:Sabareesh Ganapathy of Bangalore IN]]

[[:Category:Chandra Gurram of Folsom CA US|Chandra Gurram of Folsom CA US]][[Category:Chandra Gurram of Folsom CA US]]

[[:Category:Chunhui Mei of San Diego CA US|Chunhui Mei of San Diego CA US]][[Category:Chunhui Mei of San Diego CA US]]

[[:Category:Yue Qi of San Diego CA US|Yue Qi of San Diego CA US]][[Category:Yue Qi of San Diego CA US]]

==DUAL PIPELINE PARALLEL SYSTOLIC ARRAY==


This abstract first appeared for US patent application 20250117359 titled 'DUAL PIPELINE PARALLEL SYSTOLIC ARRAY

==Original Abstract Submitted==

a processing apparatus described herein includes a general-purpose parallel processing engine comprising a systolic array having multiple pipelines, each of the multiple pipelines including multiple pipeline stages, wherein the multiple pipelines include a first pipeline, a second pipeline, and a common input shared between the first pipeline and the second pipeline.



[[Category:G06F9/38]]
[[Category:G06F9/30]]
[[Category:CPC_G06F15/8046]]