View source for Intel corporation (20240345969). DYNAMICALLY INSERT TIMING AND VOLTAGE OFFSET CONTROL (VOC) OFFSETS IN INPUT/OUTPUT (IO) DURING FUNCTIONAL TRAFFIC simplified abstract

=DYNAMICALLY INSERT TIMING AND VOLTAGE OFFSET CONTROL (VOC) OFFSETS IN INPUT/OUTPUT (IO) DURING FUNCTIONAL TRAFFIC=


==Organization Name==

[[:Category:intel corporation|intel corporation]]


[[Category:intel corporation]]

==Inventor(s)==

[[:Category:Diyanesh Babu Chinnakkonda Vidyapoornachary of Austin TX (US)|Diyanesh Babu Chinnakkonda Vidyapoornachary of Austin TX (US)]][[Category:Diyanesh Babu Chinnakkonda Vidyapoornachary of Austin TX (US)]]

[[:Category:Tonia M. Rose of Wendell NC (US)|Tonia M. Rose of Wendell NC (US)]][[Category:Tonia M. Rose of Wendell NC (US)]]

==DYNAMICALLY INSERT TIMING AND VOLTAGE OFFSET CONTROL (VOC) OFFSETS IN INPUT/OUTPUT (IO) DURING FUNCTIONAL TRAFFIC - A simplified explanation of the abstract==


This abstract first appeared for US patent application 20240345969 titled 'DYNAMICALLY INSERT TIMING AND VOLTAGE OFFSET CONTROL (VOC) OFFSETS IN INPUT/OUTPUT (IO) DURING FUNCTIONAL TRAFFIC

'''Simplified Explanation''': 
The memory subsystem described in the patent application includes a reserved memory space for margining traffic, allowing for the testing of different settings to improve error rates.

* The memory controller selects the reserved memory space by setting a rank bit.
* The physical interface is configured with different settings for testing purposes.
* The system can switch between operational IO settings and margining IO settings at runtime.
* If margining IO settings show better error rates, the memory controller can reconfigure the operational IO settings.

'''Key Features and Innovation''':
* Reserved memory space for margining traffic.
* Dynamic selection of memory space using a rank bit.
* Configurable physical interface with different settings.
* Ability to switch between operational and margining IO settings.
* Automatic reconfiguration based on error rates.

'''Potential Applications''':
The technology can be used in various memory systems to improve error rates and optimize performance.

'''Problems Solved''':
The technology addresses the need for efficient testing of memory subsystems and the improvement of error rates in memory operations.

'''Benefits''':
* Improved error rates in memory operations.
* Dynamic selection and configuration of memory space.
* Enhanced performance optimization.

'''Commercial Applications''':
This technology can be applied in data centers, servers, and other computing systems where memory performance is critical for overall system efficiency.

'''Prior Art''':
Readers can explore prior research on memory subsystem testing and error rate optimization in memory operations.

'''Frequently Updated Research''':
Stay informed about the latest developments in memory subsystem technology and error rate optimization for memory operations.

'''Questions about Memory Subsystem Technology''':
1. How does the technology improve error rates in memory operations?
2. What are the potential applications of this technology in different computing systems?


==Original Abstract Submitted==

a memory subsystem includes a memory space reserved for margining traffic. the memory controller sets a rank bit to select the reserved memory space and configures a physical interface with different settings to test. thus, the system can have operational io (input/output) settings and margining io settings that can both be used at runtime. if the margining io settings provide an improved error rate over the operational io settings, the memory controller can reconfigure the operation io settings.



[[Category:G06F13/16]]
[[Category:CPC_G06F13/1668]]