View source for Intel corporation (20240162141). SIDEWAYS VIAS IN ISOLATION AREAS TO CONTACT INTERIOR LAYERS IN STACKED DEVICES simplified abstract

=SIDEWAYS VIAS IN ISOLATION AREAS TO CONTACT INTERIOR LAYERS IN STACKED DEVICES=


==Organization Name==

[[:Category:intel corporation|intel corporation]]


[[Category:intel corporation]]

==Inventor(s)==

[[:Category:Ehren Mannebach of Beaverton OR (US)|Ehren Mannebach of Beaverton OR (US)]][[Category:Ehren Mannebach of Beaverton OR (US)]]

[[:Category:Aaron Lilak of Beaverton OR (US)|Aaron Lilak of Beaverton OR (US)]][[Category:Aaron Lilak of Beaverton OR (US)]]

[[:Category:Hui Jae Yoo of Portland OR (US)|Hui Jae Yoo of Portland OR (US)]][[Category:Hui Jae Yoo of Portland OR (US)]]

[[:Category:Patrick Morrow of Portland OR (US)|Patrick Morrow of Portland OR (US)]][[Category:Patrick Morrow of Portland OR (US)]]

[[:Category:Anh Phan of Beaverton OR (US)|Anh Phan of Beaverton OR (US)]][[Category:Anh Phan of Beaverton OR (US)]]

[[:Category:Willy Rachmady of Beaverton OR (US)|Willy Rachmady of Beaverton OR (US)]][[Category:Willy Rachmady of Beaverton OR (US)]]

[[:Category:Cheng-Ying Huang of Portland OR (US)|Cheng-Ying Huang of Portland OR (US)]][[Category:Cheng-Ying Huang of Portland OR (US)]]

[[:Category:Gilbert Dewey of Beaverton OR (US)|Gilbert Dewey of Beaverton OR (US)]][[Category:Gilbert Dewey of Beaverton OR (US)]]

[[:Category:Rishabh Mehandru of Portland OR (US)|Rishabh Mehandru of Portland OR (US)]][[Category:Rishabh Mehandru of Portland OR (US)]]

==SIDEWAYS VIAS IN ISOLATION AREAS TO CONTACT INTERIOR LAYERS IN STACKED DEVICES - A simplified explanation of the abstract==


This abstract first appeared for US patent application 20240162141 titled 'SIDEWAYS VIAS IN ISOLATION AREAS TO CONTACT INTERIOR LAYERS IN STACKED DEVICES

==Simplified Explanation==

The abstract of the patent application describes electronic systems with vias that have both horizontal and vertical portions to provide interconnects to stacked components. 

* Electronic systems have vias with horizontal and vertical portions for interconnects to stacked components.
* The system includes a board, a package substrate, and a die with a stack of components.
* The via adjacent to the stack of components has a vertical and horizontal portion for connectivity.

== Potential Applications ==
This technology could be applied in:
* High-density electronic devices
* Stacked component systems
* Miniaturized electronics

== Problems Solved ==
This technology helps in:
* Improving connectivity in stacked components
* Enhancing signal transmission efficiency
* Reducing space requirements in electronic systems

== Benefits ==
The benefits of this technology include:
* Increased performance in electronic systems
* Enhanced reliability of interconnects
* Greater design flexibility in stacked component configurations

== Potential Commercial Applications ==
The potential commercial applications of this technology could be in:
* Consumer electronics
* Telecommunications equipment
* Automotive electronics

== Possible Prior Art ==
One possible prior art for this technology could be the use of through-silicon vias (TSVs) in stacked die configurations.

=== What are the manufacturing processes involved in creating the vias with horizontal and vertical portions?
The manufacturing processes involved in creating the vias with horizontal and vertical portions include specialized drilling and plating techniques to achieve the desired structure.

=== How does the presence of vias with both horizontal and vertical portions impact the overall performance of the electronic system?
The presence of vias with both horizontal and vertical portions improves signal transmission efficiency, reduces signal interference, and enables higher density stacking of components in the electronic system.


==Original Abstract Submitted==

embodiments disclosed herein include electronic systems with vias that include a horizontal and vertical portion in order to provide interconnects to stacked components, and methods of forming such systems. in an embodiment, an electronic system comprises a board, a package substrate electrically coupled to the board, and a die electrically coupled to the package substrate. in an embodiment the die comprises a stack of components, and a via adjacent to the stack of components, wherein the via comprises a vertical portion and a horizontal portion.



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