View source for Intel Corporation patent applications on 2025-05-15

=Patent Applications by Intel Corporation on May 15th, 2025=

[[:Category:Intel Corporation|Intel Corporation]]: 17 patent applications[[Category:Intel Corporation]]

Intel Corporation has applied for patents in the areas of [[:Category:CPC_B60W30/0956|B60W30/0956]] (CONJOINT CONTROL OF VEHICLE SUB-UNITS OF DIFFERENT TYPE OR DIFFERENT FUNCTION; CONTROL SYSTEMS SPECIALLY ADAPTED FOR HYBRID VEHICLES; ROAD VEHICLE DRIVE CONTROL SYSTEMS FOR PURPOSES NOT RELATED TO THE CONTROL OF A PARTICULAR SUB-UNIT, 1), [[:Category:CPC_H04B7/0695|H04B7/0695]] (at the transmitting station, 1), [[:Category:CPC_H10D62/121|H10D62/121]] (No explanation available, 1), [[:Category:CPC_H10D30/6735|H10D30/6735]] (No explanation available, 1), [[:Category:CPC_H10D30/6713|H10D30/6713]] (No explanation available, 1), [[:Category:CPC_H04W12/06|H04W12/06]] (Authentication, 1), [[:Category:CPC_H04N23/667|H04N23/667]] (PICTORIAL COMMUNICATION, e.g. TELEVISION, 1), [[:Category:CPC_H04L1/0045|H04L1/0045]] ({Arrangements at the receiver end}, 1), [[:Category:CPC_H02J7/06|H02J7/06]] (CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY, 1), [[:Category:CPC_G06F9/4881|G06F9/4881]] (Program initiating; Program switching, e.g. by interrupt, 1)

With keywords such as: plurality, memory, over, trajectory, pedestrian, apparatus, comprising, observed, locations, store in patent application abstracts.

Top Inventors:
* [[:Category:David Gomez Gutierrez of Tlaquepaque  MX|David Gomez Gutierrez of Tlaquepaque  MX]] (1 patents)
* [[:Category:Javier Felip Leon of Hillsboro OR US|Javier Felip Leon of Hillsboro OR US]] (1 patents)
* [[:Category:Kshitij A. Doshi of Tempe AZ US|Kshitij A. Doshi of Tempe AZ US]] (1 patents)
* [[:Category:Leobardo E. Campos Macias of Guadalajara  MX|Leobardo E. Campos Macias of Guadalajara  MX]] (1 patents)
* [[:Category:Nilesh Amar Ahuja of Cupertino CA US|Nilesh Amar Ahuja of Cupertino CA US]] (1 patents)

====Patent Applications by Intel Corporation====

[[20250153712. AN APPARATUS COMPRISING A MEMORY TO STOR_simplified_abstract_(intel corporation)]]

Abstract: an apparatus comprising a memory to store an observed trajectory of a pedestrian, the observed trajectory comprising a plurality of observed locations of the pedestrian over a first plurality of timesteps; and a processor to generate a predicted trajectory of the pedestrian, the predicted trajectory comprising a plurality of predicted locations of the pedestrian over the first plurality of timesteps and over a second plurality of timesteps occurring after the first plurality of timesteps; determine a likelihood of the predicted trajectory based on a comparison of the plurality of predicted locations of the pedestrian over the first plurality of timesteps and the plurality of observed locations of the pedestrian over the first plurality of timesteps; and responsive to the determined likelihood of the predicted trajectory, provide information associated with the predicted trajectory to a vehicle to warn the vehicle of a potential collision with the pedestrian.
[[Category:intel corporation]]

[[20250156222. APPARATUSES TO SYNCHRONIZE LANES THAT DI_simplified_abstract_(intel corporation)]]

Abstract: apparatuses to synchronize lanes that diverge or threads that drift are disclosed. in one embodiment, a graphics multiprocessor includes a queue having an initial state of groups with a first group having threads of first and second instruction types and a second group having threads of the first and second instruction types. a regroup engine (or regroup circuitry) regroups threads into a third group having threads of the first instruction type and a fourth group having threads of the second instruction type.
[[Category:intel corporation]]

[[20250156356. EXAMPLES INCLUDE TECHNIQUES TO UTILIZE N_simplified_abstract_(intel corporation)]]

Abstract: examples include techniques to utilize near memory compute circuitry for memory-bound workloads. examples include the near memory compute circuitry being resident on an input/output (i/o) arranged to couple with a plurality of memory devices configured as a memory pool that is accessible to a host central processing unit (cpu) through the i/o switch. the near memory compute circuitry may receive a request to obtain data from the memory pool and generate a result that is made available to the host cpu to facilitate acceleration of a memory-bound workload.
[[Category:intel corporation]]

[[20250156366. A METHOD AND SYSTEM FOR OPTIMIZING OVERA_simplified_abstract_(intel corporation)]]

Abstract: a method and system for optimizing overall throughput of a peripheral component interconnect express (pcie)/compute express link (cxl) host bridge. the pcie/cxl host bridge includes a plurality of ports, and one or more devices are connected to the ports. credits are initially allocated to the ports of the pcie/cxl host bridge. a link status on the ports of the pcie/cxl host bridge and/or a status of scheduled workloads on a host are then determined. the credits allocated to the ports of the pcie/cxl host bridge are adjusted based on the link status and/or the status of scheduled workloads. a pcie driver may detect the link status of each port of the pcie/cxl host bridge and request to adjust the credits based on the link status. an orchestration software that is configured to schedule and switch workloads may request to adjust the credits based on the status of scheduled workloads.
[[Category:intel corporation]]

[[20250156371. METHODS AND APPARATUS RELATING TO DATA I_simplified_abstract_(intel corporation)]]

Abstract: methods and apparatus relating to data initialization techniques. in an example, an apparatus comprises a processor to read one or more metadata codes which map to one or more cache lines in a cache memory and invoke a random number generator to generate random numerical data for the one or more cache lines in response to a determination that the one more metadata codes indicate that the cache lines are to contain random numerical data. other embodiments are also disclosed and claimed.
[[Category:intel corporation]]

[[20250157808. METHODS AND APPARATUS UTILIZING INDIUM-B_simplified_abstract_(intel corporation)]]

Abstract: methods and apparatus utilizing indium-based precursors in semiconductor manufacturing are disclosed. an example apparatus includes a substrate layer, the substrate layer to be included an integrated circuit package, and a photoresist on the substrate layer, the photoresist including indium.
[[Category:intel corporation]]

[[20250157941. MICROELECTRONIC ASSEMBLIES, RELATED DEVI_simplified_abstract_(intel corporation)]]

Abstract: microelectronic assemblies, related devices and methods, are disclosed herein. in some embodiments, a microelectronic assembly may include a package substrate including a first conductive pathway; a mold material on the package substrate including a first microelectronic component embedded in the mold material, a second microelectronic component embedded in the mold material, and a tmv, between the first and second microelectronic components, the tmv electrically coupled to the first conductive pathway; a redistribution layer (rdl) on the mold material including a second conductive pathway electrically coupled to the tmv; and a third microelectronic component on the rdl and electrically coupled to the second conductive pathway, wherein the second conductive pathway electrically couples the tmv, the first microelectronic component, and the third microelectronic component.
[[Category:intel corporation]]

[[20250158269. DISCLOSED HEREIN ARE INTEGRATED CIRCUIT _simplified_abstract_(intel corporation)]]

Abstract: disclosed herein are integrated circuit (ic) packages, antenna boards, antenna modules, and communication devices (e.g., for millimeter wave communications). for example, in some embodiments, an antenna module may include: a logic die; a radio frequency front-end (rffe) die in electrical communication with the logic die; and an antenna patch, wherein the rffe die is closer to the antenna patch than the logic die is to the antenna patch.
[[Category:intel corporation]]

[[20250158442. THE DISCLOSURE PROVIDES A DEVICE, INCLUD_simplified_abstract_(intel corporation)]]

Abstract: the disclosure provides a device, including: an ac source interface to be coupled to an ac source; a battery interface to be coupled to a battery to be charged by the ac source and discharged for supplying power to the device; and a trigger module to trigger a power supply mode for the device based on a battery-related condition and a device-related condition, wherein the power supply mode includes a reversal power supply mode of using the battery as a primary power source for the device and using the ac source as a secondary power source for the device when the ac source and the battery are both available for providing power to the device.
[[Category:intel corporation]]

[[20250158687. METHODS, SYSTEMS, AND STORAGE MEDIA ARE _simplified_abstract_(intel corporation)]]

Abstract: methods, systems, and storage media are described for beam management for higher-frequency systems, such as, for example, those above 52.6 ghz. other embodiments may be described and/or claimed.
[[Category:intel corporation]]

[[20250158738. SYSTEMS AND APPARATUSES CAN INCLUDE A RE_simplified_abstract_(intel corporation)]]

Abstract: systems and apparatuses can include a receiver that includes port to receive a flow control unit (flit) across a link, the link comprising a plurality of lanes. the receiver can also include error detection circuitry to determine an error in the flit, an error counter to count a number of errors received, the error counter to increment based on an error detected in the flit by the error detection circuitry, a flit counter to count a number of flits received, the flit counter to increment based on receiving a flit, and bit error rate logic to determine a bit error rate based on a count recorded by the error counter and a number of bits received as indicated by the flit counter. the systems and apparatuses can apply processes to perform direct ber measurements at the receiver.
[[Category:intel corporation]]

[[20250159343. METHODS, SYSTEMS, AND APPARATUS ARE DISC_simplified_abstract_(intel corporation)]]

Abstract: methods, systems, and apparatus are disclosed to select among image sensors based on device orientation. an example electronic device comprising a device orientation sensor, a first image sensor, a second image sensor, and processor circuitry to execute instructions to determine a detected orientation of the electronic device based on data from the device orientation sensor, select one of the first image sensor or the second image sensor based on the detected orientation of the electronic device, the first image sensor associated with a first orientation of the electronic device, the second image sensor associated with a second orientation of the electronic device, and activate the selected one of the first image sensor or the second image sensor to collect image data.
[[Category:intel corporation]]

[[20250159475. PROVIDED IS A COMPUTER-READABLE MEDIUM I_simplified_abstract_(intel corporation)]]

Abstract: provided is a computer-readable medium including computer-readable instructions. when the instructions are executed by a computer, the computer may implement a method. according to this method, a first group of distance-related information associated with a first proximity detection device and a user over a period of time is obtained. furthermore, based on the first group of distance-related information, first proximity information indicating whether the first proximity detection device is proximate to the user is determined. moreover, the first proximity information is used for authentication.
[[Category:intel corporation]]

[[20250159927. INTEGRATED CIRCUIT STRUCTURES HAVING PAR_simplified_abstract_(intel corporation)]]

Abstract: integrated circuit structures having partitioned source or drain contact structures, and methods of fabricating integrated circuit structures having partitioned source or drain contact structures, are described. for example, an integrated circuit structure includes a fin. a gate stack is over the fin. a first epitaxial source or drain structure is at a first end of the fin. a second epitaxial source or drain structure is at a second end of the fin. a conductive contact structure is coupled to one of the first or the second epitaxial source or drain structures. the conductive contact structure has a first portion partitioned from a second portion.
[[Category:intel corporation]]

[[20250159932. INTEGRATED CIRCUIT STRUCTURES HAVING MET_simplified_abstract_(intel corporation)]]

Abstract: integrated circuit structures having metal gate cut plug structures are described. for example, an integrated circuit structure includes a vertical stack of horizontal nanowires. a gate electrode is over the vertical stack of horizontal nanowires. a conductive trench contact is adjacent to the gate electrode. a dielectric sidewall spacer is between the gate electrode and the conductive trench contact. a dielectric cut plug structure extends through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact. the dielectric cut plug structure includes silicon and oxygen, with oxygen in direct contact with a metal-containing layer of the gate electrode.
[[Category:intel corporation]]

[[20250159953. IC DEVICES WITH ANGLED TRANSISTORS, AND _simplified_abstract_(intel corporation)]]

Abstract: ic devices with angled transistors, and related assemblies and methods, are disclosed herein. a transistor is referred to as “angled” if a longitudinal axis of an elongated semiconductor structure (e.g., a fin or a nanoribbon) based on which the transistor is built is at an angle other than 0 degrees or 90 degrees with respect to edges of front or back faces of a support structure on/in which the transistor resides, e.g., at an angle between 10 degrees and 80 degrees with respect to at least one of such edges. angled transistors provide a promising way to increasing densities of transistors on the limited real estate of semiconductor chips.
[[Category:intel corporation]]

[[20250160059. A MICRO-LED INCLUDES A LIGHT EMITTER BET_simplified_abstract_(intel corporation)]]

Abstract: a micro-led includes a light emitter between a pair of reflective metasurfaces formed from nanostructures. the metasurfaces have different levels of reflectivity, with one metasurface reflecting nearly all light, and the other metasurface allowing some light to pass through. the reflections of the light within the micro-led result in an improved radiation recombination rate, which results in an increased modulation speed. in addition, the light emitted from the micro-led has a relatively narrow divergence angle and narrow emission linewidth, making the micro-led suitable for optical communications.
[[Category:intel corporation]]