View source for Category:Hosadurga Shobha of Niskayuna NY (US)

== Hosadurga Shobha of Niskayuna NY (US) ==

=== Executive Summary ===
Hosadurga Shobha of Niskayuna NY (US) is an inventor who has filed 1 patents. Their primary areas of innovation include {by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating  (plating on semiconductors in general (1 patents), SEMICONDUCTOR DEVICES NOT COVERED BY CLASS (1 patents), {formation of thin insulating films on the sidewalls or on top of conductors  ( (1 patents), and they have worked with companies such as Adeia Semiconductor Solutions LLC (1 patents). Their most frequent collaborators include [[Category:Daniel C. Edelstein of White Plains NY (US)|Daniel C. Edelstein of White Plains NY (US)]] (1 collaborations), [[Category:Son V. Nguyen of Schenectady NY (US)|Son V. Nguyen of Schenectady NY (US)]] (1 collaborations), [[Category:Takeshi Nogami of Schenectady NY (US)|Takeshi Nogami of Schenectady NY (US)]] (1 collaborations).

=== Patent Filing Activity ===
[[File:Hosadurga_Shobha_of_Niskayuna_NY_(US)_Monthly_Patent_Applications.png|border|800px]]

=== Technology Areas ===
[[File:Hosadurga_Shobha_of_Niskayuna_NY_(US)_Top_Technology_Areas.png|border|800px]]

==== List of Technology Areas ====
* [[:Category:CPC_H01L21/76879|H01L21/76879]] ({by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating  (plating on semiconductors in general): 1 patents
* [[:Category:CPC_H01L2924/0002|H01L2924/0002]] (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
* [[:Category:CPC_H01L21/76834|H01L21/76834]] ({formation of thin insulating films on the sidewalls or on top of conductors  (): 1 patents
* [[:Category:CPC_H01L21/76831|H01L21/76831]] ({in via holes or trenches, e.g. non-conductive sidewall liners}): 1 patents
* [[:Category:CPC_H01L21/76855|H01L21/76855]] ({After-treatment introducing at least one additional element into the layer}): 1 patents
* [[:Category:CPC_H01L21/02068|H01L21/02068]] ({during, before or after processing of insulating layers}): 1 patents
* [[:Category:CPC_H01L23/528|H01L23/528]] ({Geometry or} layout of the interconnection structure {(): 1 patents
* [[:Category:CPC_H01L23/53238|H01L23/53238]] (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
* [[:Category:CPC_H01L21/76802|H01L21/76802]] (Applying interconnections to be used for carrying current between separate components within a device {comprising conductors and dielectrics}): 1 patents
* [[:Category:CPC_H01L21/7684|H01L21/7684]] (Applying interconnections to be used for carrying current between separate components within a device {comprising conductors and dielectrics}): 1 patents
* [[:Category:CPC_H01L21/76843|H01L21/76843]] ({formed in openings in a dielectric}): 1 patents
* [[:Category:CPC_H01L21/76858|H01L21/76858]] ({by diffusing alloying elements}): 1 patents
* [[:Category:CPC_H01L21/76865|H01L21/76865]] ({Selective removal of parts of the layer  (): 1 patents
* [[:Category:CPC_H01L21/76873|H01L21/76873]] ({Thin films associated with contacts of capacitors}): 1 patents
* [[:Category:CPC_H01L21/76888|H01L21/76888]] ({by deposition over sacrificial masking layer, e.g. lift-off  (lift-off per se): 1 patents
* [[:Category:CPC_H01L23/5226|H01L23/5226]] (SEMICONDUCTOR DEVICES NOT COVERED BY CLASS): 1 patents
* [[:Category:CPC_H01L21/02172|H01L21/02172]] ({the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides  (materials containing silicon): 1 patents
* [[:Category:CPC_H01L21/02244|H01L21/02244]] ({the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides  (adhesion layers or buffer layers): 1 patents
* [[:Category:CPC_H01L21/76846|H01L21/76846]] ({Layer combinations}): 1 patents
* [[:Category:CPC_H01L21/7685|H01L21/7685]] ({the layer covering a conductive structure  (): 1 patents
* [[:Category:CPC_H01L21/76856|H01L21/76856]] ({by treatment in plasmas or gaseous environments, e.g. nitriding a refractory metal liner}): 1 patents
* [[:Category:CPC_H01L21/76849|H01L21/76849]] ({the layer being positioned on top of the main fill metal}): 1 patents

=== Companies ===
[[File:Hosadurga_Shobha_of_Niskayuna_NY_(US)_Top_Companies.png|border|800px]]

==== List of Companies ====
* Adeia Semiconductor Solutions LLC: 1 patents

=== Collaborators ===
* [[:Category:Daniel C. Edelstein of White Plains NY (US)|Daniel C. Edelstein of White Plains NY (US)]][[Category:Daniel C. Edelstein of White Plains NY (US)]] (1 collaborations)
* [[:Category:Son V. Nguyen of Schenectady NY (US)|Son V. Nguyen of Schenectady NY (US)]][[Category:Son V. Nguyen of Schenectady NY (US)]] (1 collaborations)
* [[:Category:Takeshi Nogami of Schenectady NY (US)|Takeshi Nogami of Schenectady NY (US)]][[Category:Takeshi Nogami of Schenectady NY (US)]] (1 collaborations)
* [[:Category:Deepika Priyadarshini of Guilderland NY (US)|Deepika Priyadarshini of Guilderland NY (US)]][[Category:Deepika Priyadarshini of Guilderland NY (US)]] (1 collaborations)

[[Category:Hosadurga Shobha of Niskayuna NY (US)]]
[[Category:Inventors]]
[[Category:Inventors filing patents with Adeia Semiconductor Solutions LLC]]