View source for 20250217149. Apparatuses, Methods, Sy (Intel)

= APPARATUSES, METHODS, AND SYSTEMS FOR INSTRUCTIONS FOR MATRIX TRANSPOSE =

'''Abstract''':
examples detailed herein at least include transpose circuitry that is external to a matrix operations accelerator. in some examples, the transpose circuitry at least includes a plurality of transpose engines to transpose a source matrix operand of a single instruction to generate a transposed source matrix, and control circuitry to direct the plurality of transpose engines to alternately operate in a parallel loading mode and a serial loading mode to generate the transposed source matrix, wherein the plurality of transposes engines and the control circuitry are at least a portion of transpose circuitry.

'''Inventor(s)''': [[:Category:Kamlesh PILLAI of Bangalore  IN|Kamlesh PILLAI]], [[:Category:Christopher J. HUGHES of Santa Clara CA US|Christopher J. HUGHES]], [[:Category:Vinay JOSHI of Maharashatra  IN|Vinay JOSHI]], [[:Category:Om Ji OMER of Bangalore  IN|Om Ji OMER]]

'''CPC Classification''': [[:Category:CPC_G06F9/30181|G06F9/30181]] ({Instruction operation extension or modification})


[[Category:Patent Applications]]
[[Category:Intel Corporation]]
[[Category:CPC_G06F9/30181]]
[[Category:Kamlesh PILLAI of Bangalore  IN]]
[[Category:Christopher J. HUGHES of Santa Clara CA US]]
[[Category:Vinay JOSHI of Maharashatra  IN]]
[[Category:Om Ji OMER of Bangalore  IN]]

[https://wikipatents.org/index.php?search=20250217149+rejection&title=Special%3ASearch&wprov=acrw1_-1 Search for rejections for patent application number 20250217149]


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