View source for 20250173393. Sparse Matrix Multiplication (XMOS)

= SPARSE MATRIX MULTIPLICATION =

'''Abstract''':
a processor and method for efficiently implementing matrix multiplication. the processor comprises: a first register (vc) for storing elements of an input vector (x); a second register (vb) for storing a plurality of index tuples, each index tuple comprising at least an input index addressing an element of the input vector (x) in the first register (vc); an output register (va) comprising a plurality of accumulators for storing elements of an output vector (v); a vector unit configured to execute each index tuple in the second register (vb) in parallel by, for each index tuple: i) generating a respective result value by multiplying the element of the input vector (x) in the first register (vc) addressed by the input index of that index tuple by a corresponding kernel weight in a memory; and ii) adding the result value for that index tuple to one of the accumulators in the output register (va).

'''Inventor(s)''': [[:Category:Hendrik Lambertus MULLER of Bristol  GB|Hendrik Lambertus MULLER]], [[:Category:Andrew STANFORD-JASON of Bristol  GB|Andrew STANFORD-JASON]]

'''CPC Classification''': [[:Category:CPC_G06F17/16|G06F17/16]] (Matrix or vector computation {, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization  (matrix transposition )})


[[Category:Patent Applications]]
[[Category:XMOS LTD]]
[[Category:CPC_G06F17/16]]
[[Category:Hendrik Lambertus MULLER of Bristol  GB]]
[[Category:Andrew STANFORD-JASON of Bristol  GB]]

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