View source for 20250166114. Architecture Block Spars (Intel)

= ARCHITECTURE FOR BLOCK SPARSE OPERATIONS ON A SYSTOLIC ARRAY =

'''Abstract''':
embodiments described herein include software, firmware, and hardware logic that provides techniques to perform arithmetic on sparse data via a systolic processing unit. one embodiment provides for data aware sparsity via compressed bitstreams. one embodiment provides for block sparse dot product instructions. one embodiment provides for a depth-wise adapter for a systolic array.

'''Inventor(s)''': [[:Category:Abhishek Appu of El Dorado Hills CA US|Abhishek Appu]], [[:Category:Subramaniam Maiyuran of Gold River CA US|Subramaniam Maiyuran]], [[:Category:Mike Macpherson of Portland OR US|Mike Macpherson]], [[:Category:Fangwen Fu of Folsom CA US|Fangwen Fu]], [[:Category:Jiasheng Chen of El Dorado Hills CA US|Jiasheng Chen]], [[:Category:Varghese George of Folsom CA US|Varghese George]], [[:Category:Vasanth Ranganathan of El Dorado Hills CA US|Vasanth Ranganathan]], [[:Category:Ashutosh Garg of Folsom CA US|Ashutosh Garg]], [[:Category:Joydeep Ray of Folsom CA US|Joydeep Ray]]

'''CPC Classification''': [[:Category:CPC_G06T1/20|G06T1/20]] (Processor architectures; Processor configuration, e.g. pipelining)


[[Category:Patent Applications]]
[[Category:Intel Corporation]]
[[Category:CPC_G06T1/20]]
[[Category:Abhishek Appu of El Dorado Hills CA US]]
[[Category:Subramaniam Maiyuran of Gold River CA US]]
[[Category:Mike Macpherson of Portland OR US]]
[[Category:Fangwen Fu of Folsom CA US]]
[[Category:Jiasheng Chen of El Dorado Hills CA US]]
[[Category:Varghese George of Folsom CA US]]
[[Category:Vasanth Ranganathan of El Dorado Hills CA US]]
[[Category:Ashutosh Garg of Folsom CA US]]
[[Category:Joydeep Ray of Folsom CA US]]

[https://wikipatents.org/index.php?search=20250166114+rejection&title=Special%3ASearch&wprov=acrw1_-1 Search for rejections for patent application number 20250166114]


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