View source for 20240086694.NEUROMORPHIC METHOD AND APPARATUS WITH MULTI-BIT NEUROMORPHIC OPERATION simplified abstract (samsung electronics co., ltd.)

=NEUROMORPHIC METHOD AND APPARATUS WITH MULTI-BIT NEUROMORPHIC OPERATION=


==Organization Name==

[[:Category:samsung electronics co., ltd.|samsung electronics co., ltd.]]


[[Category:samsung electronics co., ltd.]]

==Inventor(s)==

[[:Category:Sungho Kim of Yongin-si (KR)|Sungho Kim of Yongin-si (KR)]][[Category:Sungho Kim of Yongin-si (KR)]]

[[:Category:Cheheung Kim of Yongin-si (KR)|Cheheung Kim of Yongin-si (KR)]][[Category:Cheheung Kim of Yongin-si (KR)]]

[[:Category:Jaeho Lee of Seoul (KR)|Jaeho Lee of Seoul (KR)]][[Category:Jaeho Lee of Seoul (KR)]]

==NEUROMORPHIC METHOD AND APPARATUS WITH MULTI-BIT NEUROMORPHIC OPERATION - A simplified explanation of the abstract==


This abstract first appeared for US patent application 20240086694 titled 'NEUROMORPHIC METHOD AND APPARATUS WITH MULTI-BIT NEUROMORPHIC OPERATION

==Simplified Explanation==

The abstract describes a neuromorphic apparatus designed to process a multi-bit neuromorphic operation. It includes a single axon circuit, a single synaptic circuit, a single neuron circuit, and a controller. The axon circuit receives an i-th bit of an n-bit axon as the first input, while the synaptic circuit stores a j-th bit of an m-bit synaptic weight as the second input and outputs a synaptic operation value. The neuron circuit calculates the result of the multi-bit operation between the axon and synaptic weight based on the synaptic operation value. The controller determines which bits are assigned to the axon and synaptic circuits for each time period.

* The neuromorphic apparatus processes multi-bit operations.
* It includes circuits for axon, synapse, neuron, and a controller.
* The axon circuit receives an i-th bit of an n-bit axon.
* The synaptic circuit stores a j-th bit of an m-bit synaptic weight and outputs a synaptic operation value.
* The neuron circuit calculates the result of the operation based on the synaptic value.
* The controller assigns bits to the circuits for processing.

== Potential Applications ==
This technology could be applied in:
* Neuromorphic computing
* Artificial intelligence
* Robotics

== Problems Solved ==
This technology helps in:
* Efficient processing of multi-bit neuromorphic operations
* Mimicking biological neural networks
* Enhancing computational capabilities

== Benefits ==
The benefits of this technology include:
* Faster processing of complex operations
* Lower power consumption
* Improved accuracy in calculations

== Potential Commercial Applications ==
The potential commercial applications of this technology could be in:
* Neuromorphic processors
* Machine learning systems
* Autonomous vehicles

== Possible Prior Art ==
One possible prior art could be:
* Research on neuromorphic computing systems
* Studies on synaptic circuits and neural networks

== Unanswered Questions ==

=== How does this technology compare to traditional computing systems? ===
This article does not provide a direct comparison between this neuromorphic apparatus and traditional computing systems. It would be interesting to know the performance differences, energy efficiency, and scalability aspects.

=== What are the limitations of this neuromorphic apparatus in terms of scalability? ===
The article does not address the scalability limitations of this technology. Understanding how well it can handle larger datasets or more complex operations would be crucial for its practical applications.


==Original Abstract Submitted==

a neuromorphic apparatus configured to process a multi-bit neuromorphic operation including a single axon circuit, a single synaptic circuit, a single neuron circuit, and a controller. the single axon circuit is configured to receive, as a first input, an i-th bit of an n-bit axon. the single synaptic circuit is configured to store, as a second input, a j-th bit of an m-bit synaptic weight and output a synaptic operation value between the first input and the second input. the single neuron circuit is configured to obtain each bit value of a multi-bit neuromorphic operation result between the n-bit axon and the m-bit synaptic weight, based on the output synaptic operation value. the controller is configured to respectively determine the i-th bit and the j-th bit to be sequentially assigned for each time period of different time periods to the single axon circuit and the single synaptic circuit.



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