View source for 20240054271. METHOD, APPARATUS AND DEVICE FOR CONSTRUCTING FPGA-BASED PROTOTYPE VERIFICATION PLATFORM AND MEDIUM simplified abstract (INSPUR SUZHOU INTELLIGENT TECHNOLOGY CO., LTD.)

=METHOD, APPARATUS AND DEVICE FOR CONSTRUCTING FPGA-BASED PROTOTYPE VERIFICATION PLATFORM AND MEDIUM=


==Organization Name==

[[:Category:INSPUR SUZHOU INTELLIGENT TECHNOLOGY CO., LTD.|INSPUR SUZHOU INTELLIGENT TECHNOLOGY CO., LTD.]]


[[Category:INSPUR SUZHOU INTELLIGENT TECHNOLOGY CO., LTD.]]

==Inventor(s)==

[[:Category:Yi Wang of Suzhou, Jiangsu (CN)|Yi Wang of Suzhou, Jiangsu (CN)]][[Category:Yi Wang of Suzhou, Jiangsu (CN)]]

==METHOD, APPARATUS AND DEVICE FOR CONSTRUCTING FPGA-BASED PROTOTYPE VERIFICATION PLATFORM AND MEDIUM - A simplified explanation of the abstract==


This abstract first appeared for US patent application 20240054271 titled 'METHOD, APPARATUS AND DEVICE FOR CONSTRUCTING FPGA-BASED PROTOTYPE VERIFICATION PLATFORM AND MEDIUM

==Simplified Explanation==

The abstract describes a method, apparatus, and device for constructing an FPGA-based prototype verification platform, as well as a medium. The method involves converting codes for constructing the platform into a gate-level netlist based on a set constraint condition, setting requirements defined by preset parameters, performing physical optimization on the netlist when timing closure is not met, and routing elements to obtain the platform.

* Converting codes for constructing an FPGA-based prototype verification platform into a gate-level netlist based on a set constraint condition
* Setting requirements defined by preset parameters to ensure timing closure is met
* Performing physical optimization on the gate-level netlist according to a set parameter optimization rule
* Routing elements in the gate-level netlist to obtain the FPGA-based prototype verification platform

Potential applications of this technology:
* FPGA-based prototype verification platforms for testing and validating hardware designs
* Accelerating the development process of electronic systems by providing a flexible and customizable verification platform

Problems solved by this technology:
* Ensuring timing closure and meeting performance requirements in FPGA-based prototype verification platforms
* Optimizing the physical placement of elements in the gate-level netlist for improved functionality

Benefits of this technology:
* Streamlining the process of constructing FPGA-based prototype verification platforms
* Enhancing the efficiency and accuracy of hardware design verification
* Facilitating the testing and validation of complex electronic systems.


==Original Abstract Submitted==

provided are a method, apparatus and device for constructing a n fpga based prototype verification platform, and a medium. the method includes: converting, based on a set constraint condition, codes for constructing an fpga-based prototype verification platform into a gate-level netlist; setting a requirement defined by preset parameters based on a value range of each parameter when timing closure is met, and when an operation result of the gate-level netlist does not meet the requirement defined by the preset parameters, performing physical optimization on the gate-level netlist according to a set parameter optimization rule, where a physical optimization process may be regarded as the process of optimizing the placement of elements in the gate-level netlist; and performing routing on elements in the gate-level netlist that meets the requirement defined by the preset parameters or the gate-level netlist subjected to the physical optimization to obtain the fpga-based prototype verification platform.



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