View source for 20240039519. DEGLITCHER WITH INTEGRATED NON-OVERLAP FUNCTION simplified abstract (Skyworks Solutions, Inc.)

=DEGLITCHER WITH INTEGRATED NON-OVERLAP FUNCTION=


==Organization Name==

[[:Category:Skyworks Solutions, Inc.|Skyworks Solutions, Inc.]]


[[Category:Skyworks Solutions, Inc.]]

==Inventor(s)==

[[:Category:Péter On�dy of Budapest (HU)|Péter On�dy of Budapest (HU)]][[Category:Péter On�dy of Budapest (HU)]]

[[:Category:András V. Horv�th of Budapest (HU)|András V. Horv�th of Budapest (HU)]][[Category:András V. Horv�th of Budapest (HU)]]

==DEGLITCHER WITH INTEGRATED NON-OVERLAP FUNCTION - A simplified explanation of the abstract==


This abstract first appeared for US patent application 20240039519 titled 'DEGLITCHER WITH INTEGRATED NON-OVERLAP FUNCTION

==Simplified Explanation==

The abstract describes a driver circuit that includes two deglitcher circuits and logic gates. The first deglitcher circuit delays a rising or falling edge of an input signal based on a mode control signal and provides a first output signal. The second deglitcher circuit receives the first output signal and further delays a rising or falling edge of the first output signal based on the mode control signal, providing a second output signal. The logic gates combine the first and second output signals to generate gate control signals for output transistors in the driver circuit. The total deglitch time, determined by the sum of the first delay and the second delay, defines the pulse width of suppressed pulses. The second delay also determines a non-overlap time, which overlaps with the total deglitch time.

* The driver circuit includes two deglitcher circuits and logic gates.
* The first deglitcher circuit delays rising or falling edges of an input signal based on a mode control signal and provides a first output signal.
* The second deglitcher circuit further delays rising or falling edges of the first output signal based on the mode control signal and provides a second output signal.
* The logic gates combine the first and second output signals to generate gate control signals for output transistors in the driver circuit.
* The total deglitch time, determined by the sum of the first delay and the second delay, defines the pulse width of suppressed pulses.
* The second delay also determines a non-overlap time, which overlaps with the total deglitch time.

Potential applications of this technology:
* This driver circuit can be used in various electronic devices that require precise control of output signals, such as microcontrollers, data communication systems, and audio amplifiers.
* It can be particularly useful in applications where glitch-free operation is critical, such as in high-speed data transmission or audio signal processing.

Problems solved by this technology:
* Glitches or unwanted pulses in output signals can cause errors or distortions in electronic systems. This driver circuit helps suppress these glitches by delaying and controlling the edges of the input and output signals.
* It solves the problem of overlapping non-overlap time and total deglitch time, ensuring proper timing and preventing signal distortions.

Benefits of this technology:
* Improved signal integrity: The driver circuit effectively suppresses glitches, ensuring clean and accurate output signals.
* Enhanced system reliability: By preventing glitches and distortions, the driver circuit helps maintain the overall reliability and performance of electronic systems.
* Flexible control: The mode control signal allows for adjustable delay times, providing flexibility in controlling the timing of the output signals.


==Original Abstract Submitted==

a driver circuit includes a first deglitcher circuit that delays a rising edge or a falling edge of an input signal according to a mode control signal and supplies a first output signal. a second deglitcher circuit receives the first output signal and delays either a rising edge or a falling edge of the first output signal by a second delay according to the mode control signal and supplies a second output signal. logic gates combine the first and second output signals to supply gate control signals for output transistors to drive the driver circuit output. a sum of the first delay and the second delay determines the total deglitch time defining a pulse width of pulses that are suppressed by the driver circuit and the second delay determines a non-overlap time. the non-overlap time overlaps in time with the total deglitch time.



[[Category:H03K3/012]]
[[Category:H03K17/687]]
[[Category:H03K19/20]]