View source for 20240028066. CONTINUOUS TIME SYNCHRONIZATION simplified abstract (B&R INDUSTRIAL AUTOMATION GMBH)

=CONTINUOUS TIME SYNCHRONIZATION=


==Organization Name==

[[:Category:B&R INDUSTRIAL AUTOMATION GMBH|B&R INDUSTRIAL AUTOMATION GMBH]]


[[Category:B&R INDUSTRIAL AUTOMATION GMBH]]

==Inventor(s)==

[[:Category:Oliver Hoeftberger of Eggelsberg (AT)|Oliver Hoeftberger of Eggelsberg (AT)]][[Category:Oliver Hoeftberger of Eggelsberg (AT)]]

[[:Category:Franz Profelt of Eggelsberg (AT)|Franz Profelt of Eggelsberg (AT)]][[Category:Franz Profelt of Eggelsberg (AT)]]

==CONTINUOUS TIME SYNCHRONIZATION - A simplified explanation of the abstract==


This abstract first appeared for US patent application 20240028066 titled 'CONTINUOUS TIME SYNCHRONIZATION

==Simplified Explanation==

The abstract describes a method and network for time synchronization between a master and slave in an interrupt-capable network component. The method involves determining a time offset between the master and slave time, adjusting the first time fraction of the offset using a time jump in the first synchronization step, and adjusting the second time fraction of the offset in successive synchronization steps using frequency alignment and/or a time jump. The second time fraction can be a non-integer multiple within a specific range of the interrupt cycle duration. The actual occurring cycle duration of the interrupt deviates from the predefined cycle duration by no more than a predefined deviation in each of the second synchronization steps.

* The patent/application describes a method for time synchronization between a master and slave in an interrupt-capable network component.
* The method involves adjusting time fractions of a determined time offset using time jumps and frequency alignment.
* The first time fraction is adjusted in the first synchronization step, while the second time fraction is adjusted in successive synchronization steps.
* The second time fraction can be a non-integer multiple within a specific range of the interrupt cycle duration.
* The actual occurring cycle duration of the interrupt deviates from the predefined cycle duration by no more than a predefined deviation in each of the second synchronization steps.

Potential applications of this technology:
* Industrial automation systems that require precise time synchronization between different components.
* Communication networks where accurate time synchronization is crucial for efficient data transmission.
* Distributed control systems that rely on synchronized clocks for coordination and synchronization of tasks.

Problems solved by this technology:
* Ensures accurate time synchronization between master and slave devices in an interrupt-capable network component.
* Reduces time offset between devices, minimizing timing errors and improving system performance.
* Enables precise coordination and synchronization of tasks in distributed systems.

Benefits of this technology:
* Improved accuracy and reliability of time synchronization in interrupt-capable network components.
* Enhanced performance and efficiency of industrial automation systems and communication networks.
* Facilitates seamless coordination and synchronization of tasks in distributed control systems.


==Original Abstract Submitted==

a method and network for time synchronization of at least one master and at least one slave, which is an interrupt-capable network component. a time offset between a master time and a slave time is determined. a first time fraction of the determined time offset is adjusted in first synchronization step(s) using a time jump. the first time fraction corresponds to an integer multiple of the cycle duration of the interrupt(s) and a second time fraction of the determined time offset is adjusted in a number of successive second synchronization steps using frequency alignment and/or a time jump. the second time fraction corresponds to a non-integer multiple from the range ]−1.0[ and ]0.1[ of cycle duration of the interrupt(s). in each of the number of second synchronization steps, an actual occurring cycle duration of the interrupt(s) deviates from the predefined cycle duration by no more than a predefined deviation.



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