View source for 18970723. MEMORY AND OPERATION METHOD THEREOF (SK hynix Inc.)

=MEMORY AND OPERATION METHOD THEREOF=


==Organization Name==

[[:Category:SK hynix Inc.|SK hynix Inc.]]


[[Category:SK hynix Inc.]]

==Inventor(s)==

[[:Category:Seung Chan Kim of Gyeonggi-do KR|Seung Chan Kim of Gyeonggi-do KR]][[Category:Seung Chan Kim of Gyeonggi-do KR]]

[[:Category:Keon Ho Lee of Gyeonggi-do KR|Keon Ho Lee of Gyeonggi-do KR]][[Category:Keon Ho Lee of Gyeonggi-do KR]]

==MEMORY AND OPERATION METHOD THEREOF==


This abstract first appeared for US patent application 18970723 titled 'MEMORY AND OPERATION METHOD THEREOF

==Original Abstract Submitted==

A memory includes: first to Nregister circuits each suitable for receiving and storing a failure address transferred from a memory controller when a corresponding selection signal of first to Nselection signals is activated, where N is an integer equal to or greater than 2; first to Nresource latch circuits suitable for storing first to Nresource signals indicating availability of the first to Nregister circuits, respectively; and a priority selection circuit suitable for activating, when two or more of the first to Nresource signals are activated, one of selection signals respectively corresponding to the activated resource signals among the first to Nselection signals.



[[Category:G11C29/00]]
[[Category:G11C7/10]]
[[Category:G11C7/20]]
[[Category:G11C29/18]]
[[Category:G11C29/44]]
[[Category:CPC_G11C29/76]]