View source for 18915492. MULTI-TILE MEMORY MANAGEMENT (Intel Corporation)

=MULTI-TILE MEMORY MANAGEMENT=


==Organization Name==

[[:Category:Intel Corporation|Intel Corporation]]


[[Category:Intel Corporation]]

==Inventor(s)==

[[:Category:Abhishek R. Appu of El Dorado Hills CA US|Abhishek R. Appu of El Dorado Hills CA US]][[Category:Abhishek R. Appu of El Dorado Hills CA US]]

[[:Category:Altug Koker of El Dorado Hills CA US|Altug Koker of El Dorado Hills CA US]][[Category:Altug Koker of El Dorado Hills CA US]]

[[:Category:Aravindh Anantaraman of Folsom CA US|Aravindh Anantaraman of Folsom CA US]][[Category:Aravindh Anantaraman of Folsom CA US]]

[[:Category:Elmoustapha Ould-ahmed-vall of Chandler AZ US|Elmoustapha Ould-ahmed-vall of Chandler AZ US]][[Category:Elmoustapha Ould-ahmed-vall of Chandler AZ US]]

[[:Category:Valentin Andrei of San Jose CA US|Valentin Andrei of San Jose CA US]][[Category:Valentin Andrei of San Jose CA US]]

[[:Category:Nicolas Galoppo Von Borries of Portland OR US|Nicolas Galoppo Von Borries of Portland OR US]][[Category:Nicolas Galoppo Von Borries of Portland OR US]]

[[:Category:Varghese George of Folsom CA US|Varghese George of Folsom CA US]][[Category:Varghese George of Folsom CA US]]

[[:Category:Mike Macpherson of Portland OR US|Mike Macpherson of Portland OR US]][[Category:Mike Macpherson of Portland OR US]]

[[:Category:Subramaniam Maiyuran of Gold River CA US|Subramaniam Maiyuran of Gold River CA US]][[Category:Subramaniam Maiyuran of Gold River CA US]]

[[:Category:Joydeep Ray of Folsom CA US|Joydeep Ray of Folsom CA US]][[Category:Joydeep Ray of Folsom CA US]]

[[:Category:Lakshminarayanan Striramassarma of Folsom CA US|Lakshminarayanan Striramassarma of Folsom CA US]][[Category:Lakshminarayanan Striramassarma of Folsom CA US]]

[[:Category:Scott Janus of Loomis CA US|Scott Janus of Loomis CA US]][[Category:Scott Janus of Loomis CA US]]

[[:Category:Brent Insko of Portland OR US|Brent Insko of Portland OR US]][[Category:Brent Insko of Portland OR US]]

[[:Category:Vasanth Ranganathan of El Dorado Hills CA US|Vasanth Ranganathan of El Dorado Hills CA US]][[Category:Vasanth Ranganathan of El Dorado Hills CA US]]

[[:Category:Kamal Sinha of Rancho Cordova CA US|Kamal Sinha of Rancho Cordova CA US]][[Category:Kamal Sinha of Rancho Cordova CA US]]

[[:Category:Arthur Hunter of Cameron Park CA US|Arthur Hunter of Cameron Park CA US]][[Category:Arthur Hunter of Cameron Park CA US]]

[[:Category:Prasoonkumar Surti of Folsom CA US|Prasoonkumar Surti of Folsom CA US]][[Category:Prasoonkumar Surti of Folsom CA US]]

[[:Category:David Puffer of Tempe AZ US|David Puffer of Tempe AZ US]][[Category:David Puffer of Tempe AZ US]]

[[:Category:James Valerio of North Plains OR US|James Valerio of North Plains OR US]][[Category:James Valerio of North Plains OR US]]

[[:Category:Ankur N. Shah of Folsom CA US|Ankur N. Shah of Folsom CA US]][[Category:Ankur N. Shah of Folsom CA US]]

==MULTI-TILE MEMORY MANAGEMENT==


This abstract first appeared for US patent application 18915492 titled 'MULTI-TILE MEMORY MANAGEMENT

==Original Abstract Submitted==

Methods and apparatus relating to techniques for multi-tile memory management. In an example, a graphics processor includes an interposer, a first chiplet coupled with the interposer, the first chiplet including a graphics processing resource and an interconnect network coupled with the graphics processing resource, cache circuitry coupled with the graphics processing resource via the interconnect network, and a second chiplet coupled with the first chiplet via the interposer, the second chiplet including a memory-side cache and a memory controller coupled with the memory-side cache. The memory controller is configured to enable access to a high-bandwidth memory (HBM) device, the memory-side cache is configured to cache data associated with a memory access performed via the memory controller, and the cache circuitry is logically positioned between the graphics processing resource and a chiplet interface.



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