View source for 18818781. PROCESSOR (Fujitsu Limited)

=PROCESSOR=


==Organization Name==

[[:Category:Fujitsu Limited|Fujitsu Limited]]


[[Category:Fujitsu Limited]]

==Inventor(s)==

[[:Category:Takahiro Shikibu of Kawasaki JP|Takahiro Shikibu of Kawasaki JP]][[Category:Takahiro Shikibu of Kawasaki JP]]

==PROCESSOR==


This abstract first appeared for US patent application 18818781 titled 'PROCESSOR

==Original Abstract Submitted==

The processor includes core circuits and a cache unit having L to LN caches (N is 3 or more). L cache has a move-in buffer including entries in which memory access instruction resulted in cache miss in L cache is stored. The move-in buffer, when issuing a normal memory request to L cache, issues a pseudo memory request to L to LN caches in parallel and receives a pseudo data response that has coherency-unsecured data from any one cache. The re-order buffer executes a normal instruction execution completion process in response to the normal data response, executes a pseudo instruction execution completion process in response to the pseudo data response, and, when the pseudo data response is a failure, rewinds an arithmetic operation circuit that speculatively executed instructions after the memory access instruction in response to the pseudo instruction execution completion process, back to a state before the speculative execution.



[[Category:G06F12/0815]]
[[Category:CPC_G06F12/0815]]