View source for 18648599. PACKAGE SUBSTRATE HAVING POROUS DIELECTRIC LAYER simplified abstract (Texas Instruments Incorporated)

=PACKAGE SUBSTRATE HAVING POROUS DIELECTRIC LAYER=


==Organization Name==

[[:Category:Texas Instruments Incorporated|Texas Instruments Incorporated]]


[[Category:Texas Instruments Incorporated]]

==Inventor(s)==

[[:Category:Jaimal Mallory Williamson of McKinney TX (US)|Jaimal Mallory Williamson of McKinney TX (US)]][[Category:Jaimal Mallory Williamson of McKinney TX (US)]]

[[:Category:Jim C. Lo of Allen TX (US)|Jim C. Lo of Allen TX (US)]][[Category:Jim C. Lo of Allen TX (US)]]

==PACKAGE SUBSTRATE HAVING POROUS DIELECTRIC LAYER - A simplified explanation of the abstract==


This abstract first appeared for US patent application 18648599 titled 'PACKAGE SUBSTRATE HAVING POROUS DIELECTRIC LAYER

The patent application describes a method of making a multilayer package substrate with dielectric layers and patterned metal layers.

* The substrate includes a top dielectric layer, a bottom dielectric layer, a top patterned metal layer, and a bottom patterned metal layer.
* At least one of the dielectric layers is porous with an average porosity of at least 5%.
* The porous dielectric layer contains a plurality of pores throughout its thickness.

Potential Applications:
* This technology can be used in the manufacturing of electronic devices such as integrated circuits and microprocessors.
* It can also be applied in the production of advanced packaging solutions for semiconductor devices.

Problems Solved:
* Provides improved electrical performance and thermal management in multilayer package substrates.
* Enhances signal integrity and reduces crosstalk between different layers.

Benefits:
* Increased efficiency and reliability of electronic devices.
* Better heat dissipation and overall performance of semiconductor components.

Commercial Applications:
* This technology has significant commercial potential in the semiconductor industry for the production of high-performance electronic devices.

Prior Art:
* Prior research in the field of multilayer package substrates and porous dielectric materials can provide valuable insights into the development of this technology.

Frequently Updated Research:
* Ongoing research in materials science and semiconductor packaging technologies may lead to further advancements in multilayer package substrates with porous dielectric layers.

Questions about Multilayer Package Substrate Technology:
1. How does the porosity of the dielectric layers impact the overall performance of the substrate?
2. What are the key considerations in the design and fabrication of multilayer package substrates with porous dielectric layers?


==Original Abstract Submitted==

A method of making a multilayer package substrate includes forming a plurality of dielectric layers including a top dielectric layer on a top side and a bottom dielectric layer on a bottom side. A top patterned metal layer is on the top dielectric layer and a bottom patterned metal layer is on the bottom dielectric layer. At least one of the top dielectric layer and the bottom dielectric layer is a porous dielectric layer having a plurality of pores including an average porosity of at least 5% averaged over its thickness.



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