View source for 18490042. MEMORY CONTROLLER PERFORMING DATA TRAINING, SYSTEM-ON-CHIP INCLUDING THE MEMORY CONTROLLER, AND OPERATING METHOD OF THE MEMORY CONTROLLER simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)

=MEMORY CONTROLLER PERFORMING DATA TRAINING, SYSTEM-ON-CHIP INCLUDING THE MEMORY CONTROLLER, AND OPERATING METHOD OF THE MEMORY CONTROLLER=


==Organization Name==

[[:Category:SAMSUNG ELECTRONICS CO., LTD.|SAMSUNG ELECTRONICS CO., LTD.]]


[[Category:SAMSUNG ELECTRONICS CO., LTD.]]

==Inventor(s)==

[[:Category:Daero Kim of Hwaseong-si (KR)|Daero Kim of Hwaseong-si (KR)]][[Category:Daero Kim of Hwaseong-si (KR)]]

[[:Category:Kyunghoi Koo of Suwon-si (KR)|Kyunghoi Koo of Suwon-si (KR)]][[Category:Kyunghoi Koo of Suwon-si (KR)]]

[[:Category:Sujeong Kim of Hwaseong-si (KR)|Sujeong Kim of Hwaseong-si (KR)]][[Category:Sujeong Kim of Hwaseong-si (KR)]]

[[:Category:Juyoung Kim of Hwaseong-si (KR)|Juyoung Kim of Hwaseong-si (KR)]][[Category:Juyoung Kim of Hwaseong-si (KR)]]

[[:Category:Sanghune Park of Seongnam-si (KR)|Sanghune Park of Seongnam-si (KR)]][[Category:Sanghune Park of Seongnam-si (KR)]]

[[:Category:Jiyeon Park of Suwon-si (KR)|Jiyeon Park of Suwon-si (KR)]][[Category:Jiyeon Park of Suwon-si (KR)]]

[[:Category:Jihun Oh of Hwaseong-si (KR)|Jihun Oh of Hwaseong-si (KR)]][[Category:Jihun Oh of Hwaseong-si (KR)]]

[[:Category:Kyoungwon Lee of Uijeongbu-si (KR)|Kyoungwon Lee of Uijeongbu-si (KR)]][[Category:Kyoungwon Lee of Uijeongbu-si (KR)]]

==MEMORY CONTROLLER PERFORMING DATA TRAINING, SYSTEM-ON-CHIP INCLUDING THE MEMORY CONTROLLER, AND OPERATING METHOD OF THE MEMORY CONTROLLER - A simplified explanation of the abstract==


This abstract first appeared for US patent application 18490042 titled 'MEMORY CONTROLLER PERFORMING DATA TRAINING, SYSTEM-ON-CHIP INCLUDING THE MEMORY CONTROLLER, AND OPERATING METHOD OF THE MEMORY CONTROLLER

==Simplified Explanation==

The abstract describes a memory controller that includes various components to compare, adjust, and correct data received through different data lines. It also includes a training circuit to perform a training operation on the data and obtain a target read reference voltage for each piece of data.

* The memory controller has a first receiver that compares a read reference voltage with data received through a first data line and outputs a first piece of data.
* A first duty adjuster is included to adjust the duty of the first piece of data.
* The controller also has a second receiver that compares the read reference voltage with data received through a second data line and outputs a second piece of data.
* A second duty adjuster is included to adjust the duty of the second piece of data.
* A training circuit is present to perform a training operation on data received through multiple data lines.
* The training circuit obtains a target read reference voltage for each piece of data and corrects the duty of each piece of data based on the level of the target read reference voltage.

Potential Applications:
* Memory controllers can be used in various electronic devices such as computers, smartphones, and gaming consoles.
* This technology can be applied in data storage systems, improving the performance and reliability of memory operations.

Problems Solved:
* The memory controller addresses the issue of data corruption or errors during memory operations by comparing and adjusting the received data.
* It solves the problem of inconsistent read reference voltage by performing a training operation and obtaining a target read reference voltage for each piece of data.

Benefits:
* Improved data accuracy and reliability in memory operations.
* Enhanced performance and efficiency of memory controllers.
* Increased overall system stability and functionality.


==Original Abstract Submitted==

A memory controller includes a first receiver configured to compare a read reference voltage with a piece of data received through a first data line and output a first piece of data; a first duty adjuster configured to adjust a duty of the first piece of data; a second receiver configured to compare the read reference voltage with a piece of data received through a second data line and output a second piece of data; a second duty adjuster configured to adjust a duty of the second piece of data; and a training circuit configured to perform a training operation on pieces of data received through a plurality of data lines, to obtain a target read reference voltage for each piece of data and correct a duty of each piece of data based on a level of the target read reference voltage for each piece of data.



[[Category:G11C11/4096]]
[[Category:G11C11/4076]]