View source for 18488916. SYNAPTIC ARRAY STRUCTURE BASED ON CMOS INTEGRATION TECHNOLOGY AND METHOD OF FABRICATING THE SYNAPTIC ARRAY STRUCTURE simplified abstract (SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION)

=SYNAPTIC ARRAY STRUCTURE BASED ON CMOS INTEGRATION TECHNOLOGY AND METHOD OF FABRICATING THE SYNAPTIC ARRAY STRUCTURE=


==Organization Name==

[[:Category:SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION|SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION]]


[[Category:SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION]]

==Inventor(s)==

[[:Category:Jong-Ho Lee of Seoul (KR)|Jong-Ho Lee of Seoul (KR)]][[Category:Jong-Ho Lee of Seoul (KR)]]

[[:Category:Min Kyu Park of Seoul (KR)|Min Kyu Park of Seoul (KR)]][[Category:Min Kyu Park of Seoul (KR)]]

[[:Category:Joon Hwang of Seoul (KR)|Joon Hwang of Seoul (KR)]][[Category:Joon Hwang of Seoul (KR)]]

[[:Category:Ryunhan Gu of Seoul (KR)|Ryunhan Gu of Seoul (KR)]][[Category:Ryunhan Gu of Seoul (KR)]]

[[:Category:Won Mook Kang of Seoul (KR)|Won Mook Kang of Seoul (KR)]][[Category:Won Mook Kang of Seoul (KR)]]

==SYNAPTIC ARRAY STRUCTURE BASED ON CMOS INTEGRATION TECHNOLOGY AND METHOD OF FABRICATING THE SYNAPTIC ARRAY STRUCTURE - A simplified explanation of the abstract==


This abstract first appeared for US patent application 18488916 titled 'SYNAPTIC ARRAY STRUCTURE BASED ON CMOS INTEGRATION TECHNOLOGY AND METHOD OF FABRICATING THE SYNAPTIC ARRAY STRUCTURE

The patent application describes a synaptic array structure that integrates TFT-type synaptic devices and CMOS peripheral circuits on a semiconductor substrate, reducing the number of masks and fabrication steps required in the process.

* TFT-type synaptic devices are arranged in an array on an isolation insulating layer, with a source, drain, semiconductor body, oxide layers, semiconductor layer for channel, TFT gate insulating layer, and TFT gate electrode.
* CMOS peripheral circuits are provided on the semiconductor substrate, along with the isolation insulating layer to isolate devices.
* The integration of TFT-type synaptic devices and CMOS peripheral circuits streamlines the fabrication process and enhances efficiency in manufacturing.

Potential Applications:
- Neuromorphic computing
- Artificial intelligence systems
- Biomedical devices for brain-machine interfaces

Problems Solved:
- Simplifies the fabrication process
- Reduces the number of masks and steps required
- Enhances the integration of synaptic devices and peripheral circuits

Benefits:
- Improved efficiency in manufacturing
- Cost-effective fabrication process
- Enhanced performance of synaptic arrays

Commercial Applications:
Title: Integration of TFT-type Synaptic Devices for Neuromorphic Computing Systems
This technology can be utilized in the development of advanced neuromorphic computing systems for various applications in artificial intelligence, robotics, and biomedical devices. The streamlined fabrication process and enhanced integration capabilities make it a valuable innovation in the field of synaptic arrays.

Questions about Integration of TFT-type Synaptic Devices for Neuromorphic Computing Systems:
1. How does the integration of TFT-type synaptic devices and CMOS peripheral circuits improve efficiency in manufacturing?
- The integration reduces the number of masks and fabrication steps required, streamlining the process and enhancing overall efficiency.
2. What are the potential applications of this technology in the field of artificial intelligence?
- This technology can be applied in artificial intelligence systems for tasks such as pattern recognition, machine learning, and data processing.


==Original Abstract Submitted==

Provided is a synaptic array structure. The synaptic array structure includes: an isolation insulating layer positioned in a predetermined area on a semiconductor substrate to isolate devices; TFT-type synaptic devices arranged in an array on an isolation insulating layer; and CMOS peripheral circuits provided on the semiconductor substrate. The TFT-type synaptic device includes: a source and a drain positioned on the isolation insulating layer; a semiconductor body positioned between the source and the drain; oxide layers positioned between the semiconductor body and the source/drain; a semiconductor layer for channel; a TFT gate insulating layer; and a TFT gate electrode. The present invention, based on CMOS integration technology, processes TFT-type synaptic devices and CMOS peripheral circuits together, thereby reducing the number of masks and fabrication steps used during the fabricating process.



[[Category:H01L27/12]]
[[Category:H01L21/8238]]
[[Category:CPC_H01L27/1207]]