View source for 18473635. METHOD OF DESIGNING MASK LAYOUT FOR IMAGE SENSOR simplified abstract (Samsung Electronics Co., Ltd.)

=METHOD OF DESIGNING MASK LAYOUT FOR IMAGE SENSOR=


==Organization Name==

[[:Category:Samsung Electronics Co., Ltd.|Samsung Electronics Co., Ltd.]]


[[Category:Samsung Electronics Co., Ltd.]]

==Inventor(s)==

[[:Category:Yujeong Sin of Suwon-si (KR)|Yujeong Sin of Suwon-si (KR)]][[Category:Yujeong Sin of Suwon-si (KR)]]

[[:Category:Daehyun Jung of Suwon-si (KR)|Daehyun Jung of Suwon-si (KR)]][[Category:Daehyun Jung of Suwon-si (KR)]]

[[:Category:Sunggon Jung of Suwon-si (KR)|Sunggon Jung of Suwon-si (KR)]][[Category:Sunggon Jung of Suwon-si (KR)]]

==METHOD OF DESIGNING MASK LAYOUT FOR IMAGE SENSOR - A simplified explanation of the abstract==


This abstract first appeared for US patent application 18473635 titled 'METHOD OF DESIGNING MASK LAYOUT FOR IMAGE SENSOR

The patent application describes a method for designing mask layouts, including preliminary and target layouts, to improve the accuracy of pattern transfer during semiconductor manufacturing processes.

* Design a preliminary mask layout defining a pixel isolation structure to isolate multiple pixels.
* Create multiple target mask layouts by inserting assist patterns into the preliminary layout.
* Develop an optical proximity correction (OPC) model based on the target layouts to enhance pattern fidelity.
* Generate mask design images using the OPC model and extract mask contour images for further analysis.
* Select target patterns and produce a final mask for pattern transfer onto a substrate.
* Form real patterns on the substrate based on the mask design.
* Choose the final pattern from the target patterns based on the formed real pattern.

Potential Applications:
- Semiconductor manufacturing
- Photolithography processes
- Mask design optimization

Problems Solved:
- Improving pattern transfer accuracy
- Enhancing pattern fidelity in semiconductor manufacturing

Benefits:
- Increased manufacturing precision
- Reduced defects in semiconductor devices
- Enhanced overall product quality

Commercial Applications:
Title: Advanced Mask Layout Design Method for Semiconductor Manufacturing
This technology can be utilized in semiconductor fabrication facilities to optimize mask layouts and improve the accuracy of pattern transfer processes, leading to higher quality semiconductor devices and reduced manufacturing defects.

Questions about the technology:
1. How does the use of assist patterns improve the accuracy of mask layouts in semiconductor manufacturing?
2. What are the key advantages of utilizing an OPC model in mask design for semiconductor fabrication processes?


==Original Abstract Submitted==

A mask layout design method includes designing a preliminary mask layout, designing a plurality of target mask layouts by inserting a plurality of preliminary assist patterns into the preliminary mask layout, generating an optical proximity correction (OPC) model based on the plurality of target mask layouts, obtaining a plurality of mask design images by using the OPC model, extracting a plurality of mask contour images, selecting a plurality of target patterns, producing a mask based on the plurality of target mask layouts, forming a real pattern on a substrate based on the mask, and selecting a final pattern from among the plurality of target patterns based on the formed real pattern. The preliminary mask layout includes a mask layout defining a pixel isolation structure that isolates a plurality of pixels, and the preliminary assist pattern has at least one of a cross or rectangular shape.



[[Category:G03F7/00]]
[[Category:CPC_G03F7/705]]