View source for 18459277. ROBUST SCHEDULING WITH GENERATIVE FLOW NETWORKS simplified abstract (QUALCOMM Incorporated)

=ROBUST SCHEDULING WITH GENERATIVE FLOW NETWORKS=


==Organization Name==

[[:Category:QUALCOMM Incorporated|QUALCOMM Incorporated]]


[[Category:QUALCOMM Incorporated]]

==Inventor(s)==

[[:Category:Corrado Rainone of Haarlem (NL)|Corrado Rainone of Haarlem (NL)]][[Category:Corrado Rainone of Haarlem (NL)]]

[[:Category:Wei David Zhang of Amsterdam (NL)|Wei David Zhang of Amsterdam (NL)]][[Category:Wei David Zhang of Amsterdam (NL)]]

[[:Category:Roberto Bondesan of London (GB)|Roberto Bondesan of London (GB)]][[Category:Roberto Bondesan of London (GB)]]

[[:Category:Markus Peschl of Amsterdam (NL)|Markus Peschl of Amsterdam (NL)]][[Category:Markus Peschl of Amsterdam (NL)]]

[[:Category:Mukul Gagrani of Milpitas CA (US)|Mukul Gagrani of Milpitas CA (US)]][[Category:Mukul Gagrani of Milpitas CA (US)]]

[[:Category:Wonseok Jeon of San Diego CA (US)|Wonseok Jeon of San Diego CA (US)]][[Category:Wonseok Jeon of San Diego CA (US)]]

[[:Category:Edward Teague of San Diego CA (US)|Edward Teague of San Diego CA (US)]][[Category:Edward Teague of San Diego CA (US)]]

[[:Category:Piero Zappi of La Jolla CA (US)|Piero Zappi of La Jolla CA (US)]][[Category:Piero Zappi of La Jolla CA (US)]]

[[:Category:Weiliang Zeng of San Diego CA (US)|Weiliang Zeng of San Diego CA (US)]][[Category:Weiliang Zeng of San Diego CA (US)]]

[[:Category:Christopher Lott of San Diego CA (US)|Christopher Lott of San Diego CA (US)]][[Category:Christopher Lott of San Diego CA (US)]]

==ROBUST SCHEDULING WITH GENERATIVE FLOW NETWORKS - A simplified explanation of the abstract==


This abstract first appeared for US patent application 18459277 titled 'ROBUST SCHEDULING WITH GENERATIVE FLOW NETWORKS

==Simplified Explanation==

The abstract describes a method for scheduling tasks in an artificial neural network on a group of processors in a hardware device, testing different schedules, and selecting the best schedule based on performance.

* The method involves generating schedules for tasks in an artificial neural network.
* Each schedule assigns tasks to specific processors in a hardware device.
* The schedules are tested on the hardware device or a model of the device.
* The best schedule is selected based on performance criteria.

== Potential Applications ==
This technology could be applied in various fields such as:
* Machine learning
* Artificial intelligence
* High-performance computing

== Problems Solved ==
This method addresses the following issues:
* Efficient task scheduling in neural networks
* Optimizing performance on hardware devices
* Automating the selection of the best schedule

== Benefits ==
The benefits of this technology include:
* Improved efficiency in task execution
* Better utilization of hardware resources
* Automated optimization of task scheduling

== Potential Commercial Applications ==
A potential commercial application of this technology could be:
* Developing software tools for optimizing neural network performance on hardware devices

== Possible Prior Art ==
One possible prior art for this technology could be:
* Existing task scheduling algorithms for parallel computing systems

=== What are the potential impacts of this technology on the field of artificial intelligence? ===

The potential impacts of this technology on the field of artificial intelligence include:
* Enhanced performance of neural networks on hardware devices
* Automation of task scheduling processes
* Improved scalability of artificial intelligence applications

=== How does this method compare to traditional task scheduling techniques in terms of efficiency and performance? ===

This method offers advantages over traditional task scheduling techniques by:
* Dynamically assigning tasks to processors based on performance testing
* Selecting the best schedule for optimal performance
* Automating the scheduling process for artificial neural networks.


==Original Abstract Submitted==

A processor-implemented method includes generating, by a scheduling model, a group of schedules from a computation graph associated with a task, each node on the computation graph being associated with an operation of an artificial neural network, each schedule of the group of schedules associating each node of the computation graph with a processor of a group of processors of a hardware device. The processor-implemented method also includes testing one or more schedules of the group of schedules on the hardware device or a model of the hardware device. The processor-implemented method further includes selecting a schedule of the one or more schedules based on testing the one or more schedules, the selected schedule satisfying a selection condition.



[[Category:G06F9/48]]