View source for 18458743. MEMORY DEVICE TRANSMITTING AND RECEIVING DATA AT HIGH SPEED AND LOW POWER simplified abstract (SAMSUNG ELECTRONICS CO., LTD.)

=MEMORY DEVICE TRANSMITTING AND RECEIVING DATA AT HIGH SPEED AND LOW POWER=


==Organization Name==

[[:Category:SAMSUNG ELECTRONICS CO., LTD.|SAMSUNG ELECTRONICS CO., LTD.]]


[[Category:SAMSUNG ELECTRONICS CO., LTD.]]

==Inventor(s)==

[[:Category:Byongmo Moon of Seoul (KR)|Byongmo Moon of Seoul (KR)]][[Category:Byongmo Moon of Seoul (KR)]]

[[:Category:Jihye Kim of Suwon-si (KR)|Jihye Kim of Suwon-si (KR)]][[Category:Jihye Kim of Suwon-si (KR)]]

[[:Category:Je Min Ryu of Seoul (KR)|Je Min Ryu of Seoul (KR)]][[Category:Je Min Ryu of Seoul (KR)]]

[[:Category:Beomyong Kil of Suwon-si (KR)|Beomyong Kil of Suwon-si (KR)]][[Category:Beomyong Kil of Suwon-si (KR)]]

[[:Category:Sungoh Ahn of Hwaseong-si (KR)|Sungoh Ahn of Hwaseong-si (KR)]][[Category:Sungoh Ahn of Hwaseong-si (KR)]]

==MEMORY DEVICE TRANSMITTING AND RECEIVING DATA AT HIGH SPEED AND LOW POWER - A simplified explanation of the abstract==


This abstract first appeared for US patent application 18458743 titled 'MEMORY DEVICE TRANSMITTING AND RECEIVING DATA AT HIGH SPEED AND LOW POWER

==Simplified Explanation==

The abstract describes a method for using a high bandwidth memory controller. Here is a simplified explanation of the abstract:

* The method involves using a clock signal with a certain frequency, a write strobe signal with a different frequency, and write command/address and write data signals based on these clock signals.
* The clock signal has a frequency that is half of the frequency of the write strobe signal.
* The write strobe signal has two cycles of pre-amble before the write data signal and two cycles of post-amble after the write data signal.

Potential applications of this technology:

* High-performance computing systems
* Graphics processing units (GPUs)
* Data centers
* Artificial intelligence and machine learning systems

Problems solved by this technology:

* Efficient utilization of high bandwidth memory
* Synchronization of different clock frequencies
* Ensuring accurate timing for write commands and data signals

Benefits of this technology:

* Improved memory controller performance
* Enhanced data transfer rates
* Reduced latency in memory operations
* Increased overall system efficiency


==Original Abstract Submitted==

A method for using a high bandwidth memory controller includes providing a clock signal having a first clock frequency, providing a write strobe signal having a second clock frequency, providing a write command/address signal based on the clock signal, and providing a write data signal based on the write strobe signal. The first clock frequency is half of the second clock frequency, the write strobe signal has two cycles of pre-amble before the write data signal, and the write strobe signal has two cycles of post-amble after the write data signal.



[[Category:G11C11/4093]]
[[Category:G06F3/06]]
[[Category:G11C11/4076]]
[[Category:G11C11/4096]]
[[Category:H01L25/18]]