View source for 18444754. NEGATIVE BIT LINE CONTROL MECHANISM simplified abstract (MEDIATEK INC.)

=NEGATIVE BIT LINE CONTROL MECHANISM=


==Organization Name==

[[:Category:MEDIATEK INC.|MEDIATEK INC.]]


[[Category:MEDIATEK INC.]]

==Inventor(s)==

[[:Category:Weinan Liao of Hsinchu City (TW)|Weinan Liao of Hsinchu City (TW)]][[Category:Weinan Liao of Hsinchu City (TW)]]

[[:Category:Jiann-Tseng Huang of Hsinchu City (TW)|Jiann-Tseng Huang of Hsinchu City (TW)]][[Category:Jiann-Tseng Huang of Hsinchu City (TW)]]

==NEGATIVE BIT LINE CONTROL MECHANISM - A simplified explanation of the abstract==


This abstract first appeared for US patent application 18444754 titled 'NEGATIVE BIT LINE CONTROL MECHANISM

The present invention describes a memory device with a memory array, IO circuitry, and a control circuit. The IO circuitry includes a write buffer and a negative voltage provider, while the control circuit includes an NBL timing control circuit.

* Memory device with memory array, IO circuitry, and control circuit
* IO circuitry includes write buffer and negative voltage provider
* Control circuit includes NBL timing control circuit
* Negative voltage provider generates negative voltage for write driver
* NBL timing control circuit generates NBL enable signal
* Memory device supplied by first and second supply voltages
* Second supply voltage higher than first supply voltage
* Negative voltage provider and NBL timing control circuit supplied by second supply voltage

Potential Applications:
- Memory devices in electronic devices
- Data storage applications
- Computing systems

Problems Solved:
- Efficient data writing in memory arrays
- Improved performance of memory devices
- Enhanced control over negative voltage generation

Benefits:
- Faster data writing speeds
- Increased reliability of memory devices
- Better overall performance in electronic systems

Commercial Applications:
Title: Advanced Memory Devices for High-Performance Computing Systems
This technology can be used in:
- High-speed data processing systems
- Server farms
- Data centers

Questions about Memory Devices:
1. How does the negative voltage provider enhance the performance of the memory device?
The negative voltage provider improves the efficiency of data writing by generating a negative voltage for the write driver, leading to faster operation.

2. What are the advantages of using two different supply voltages in the memory device?
Using two supply voltages allows for better control over the negative voltage generation and overall performance of the memory device.


==Original Abstract Submitted==

The present invention provides a memory device including a memory array, an IO circuitry and a control circuit. The IO circuitry includes a write buffer and a negative voltage provider. The write driver is configured to receive input data to drive bit lines of the memory array, and the negative voltage provider is configured to generate to generate a negative voltage to the write driver. The control circuit includes an NBL timing control circuit configured to generate an NBL enable signal to selectively enable the negative voltage provider. In addition, the memory device is supplied by a first supply voltage and a second supply voltage, a voltage level of the second supply voltage is higher than a voltage level of the first supply voltage, and the negative voltage provider and the NBL timing control circuit are supplied by the second supply voltage.



[[Category:G11C11/419]]
[[Category:CPC_G11C11/419]]